Table 1. Design Parameters

11.2.1.2.1 Power Handling Curves

The power handling curves give the maximum output power that can be handled by the devices versus the ambient temperature. These curves give the maximum output power achievable considering that the losses inside the device can cause rise of the junction temperature up to 125°C. The thermal resistance junction to ambient were provided with considerations to two different values. Thermal resistances values of 50°C /W and of 100°C / W were considered.

The device handling capability depends on the overall design and input and output voltage. Figure 36 and Figure 38 refer to a wide-range input voltage (90 V_AC; 264 V_AC) converter; Figure 37 and Figure 39 refer to a European range input voltage (180 V_AC; 265 V_AC). The dotted line curves refer to 12-V output voltage AC-to-DC converter, the continuous line curves refer to 5-V output voltage converter.

Figure 36 and Figure 37 show the power handling capabilities of UCC28910 and Figure 38 and Figure 39 show the power handling capabilities of UCC28911.

The curves provided show the maximum power obtained through optimized designs.

A lower-efficiency design requires the converter to process more input power to deliver the same amount of power to the load. Therefore, less power handling capability is expected for lower-efficiency designs.

Figure 36. [90; 264] VRMS Input Voltage Range,
(maximum input power vs ambient temperature of UCC28910)

Figure 38. 90 V_RMS, 264 V_RMS Input Voltage Range,
(maximum output power vs ambient temperature of UCC28911)

Figure 37. [180; 264] VRMS Input Voltage Range,
(maximum input power vs ambient temperature of UCC28910)

Figure 39. 180 V_RMS, 264 V_RMS Input Voltage Range,
(maximum output power vs ambient temperature of UCC28911)

11.2.1.2.2 Input Stage Design and Bulk Capacitance

The input stage consists of:

1. Input fuse resistor (R_IN) is generally used to:
   1. Limit the inrush current on the input capacitor when the line voltage is applied.
   2. Disconnect the line in case of input over current.
2. A bridge diode or a single-wave rectifier diode used to rectify the main voltage.
3. A bulk capacitor (capacitors C1 and C2) that stores the energy and reduces input voltage ripple.
4. A line filter (L1, L2, R1, and R2) to reduce EMI generated by switching.

The minimum input capacitance voltage, the input power of the converter based on target full-load efficiency, minimum input RMS voltage, and minimum AC input frequency are used to determine the input capacitance requirement.

The maximum converter input power can be estimated from the output voltage in voltage constant mode, V_OCV, the converter's output current when operating in constant current more, I_OCC, and the full-load efficiency target, η.

Equation 6.

The following equation provides an accurate solution for input capacitance based on a target minimum bulk capacitor voltage. To target a given input capacitance value, iterate the minimum capacitor voltage to achieve the target capacitance.

Equation 7.

In the case where the input rectifier is a single diode (half wave rectifier) , and for applications with bridge input rectifier (full wave rectifier), as in the schematic of Figure 31.

The voltage V_BULK(min) is generally selected around 65% to 60% of √2 x V_IN(min). V_BULK(min) is determined by the selection of the high-voltage input capacitors.

For the considered example we have:

Equation 8.

Equation 9.

Taking into account that electrolytic capacitance, with 20% of tolerance, the values selected for C1 and C2 are: C1 = 6.8 μF and C2 = 10 μF.

11.2.1.2.3 Transformer Turns Ratio

The maximum primary-to-secondary turns ratio can be determined by the target maximum switching frequency at full load, the minimum input capacitor bulk voltage, and the estimated DCM quasi-resonant time. Initially determine the maximum available total duty cycle of the on-time and secondary conduction time based on target switching frequency and DCM resonant time. For DCM resonant time, assume t_R = 1 / 500 kHz if you do not have an estimate from previous designs. For the transition mode operation limit, the period required from the end of secondary current conduction to the first valley of the V_DS voltage is half of the DCM resonant period, or 1 μs assuming 500-kHz resonant frequency. D_MAX can be determined using the equation below.

Equation 10.

Where K_CC is the regulation gain in constant current control mode and is equal to the secondary diode conduction duty cycle when the converter is operating at maximum output current.

Once D_MAX is known, the maximum turn ratio of the primary-to-secondary can be determined with the equation below.

Equation 11.

The total voltage on the secondary winding needs to be determined; the sum of V_OCV and the secondary rectifier V_F. The voltage V_BULK(min) is generally selected around 65% or 60% of the peak of low-line. V_BULK(min) is determined by the selection of the high-voltage input capacitors.

For the 5-V USB charger applications N_PS values from 13 to 17 are typically used.

For our example the maximum value for primary to secondary turn ratio will be:

Equation 12.

In this example we fix N_PS = 16.5

In order to calculate the primary to auxiliary turn ratio (N_PA) we use the parameter V_OCC(min) that is the minimum output voltage at which we want to guarantee the output current regulation.

Equation 13.

In the example:

Equation 14.

In Equation 13 V_FAUX is the D3 diode voltage drop when conducting. The value of N_PA is generally under-estimated and the number of auxiliary winding turns can be reduced with respect to the value provided by Equation 13. Optimization can be done directly on the circuit verifying the margin between the VDD's measured value and VDD_OFF(max).

11.2.1.2.4 Output Capacitance

The output capacitance value is typically determined by the transient response requirement from no load. For example, in USB charger applications, it is often required to maintain a minimum output voltage of 4.1 V with a load-step transient from 0 mA to 500 mA (I_TRAN). The equation below assumes that the switching frequency is at the minimum of f_SW(min).

Equation 15.

Equation 16.

Another consideration on the output capacitor(s) is the ripple voltage requirement which is reviewed based on secondary-peak current and ESR. A margin of 20% is added to the capacitor ESR requirement in the equation below.

Equation 17.

V_RIPPLE is the maximum output-voltage ripple allowed for the design. The UCC2891x devices incorporates internal voltage-loop compensation circuits so that external compensation is not necessary, provided that the value of C_OUT is high enough. The following equation determines a minimum value of C_OUT necessary to maintain a phase margin >30 degrees over the full-load range.

Equation 18.

11.2.1.2.5 VDD Capacitance, C_VDD

The capacitance on VDD needs to supply the device operating current until the output of the converter reaches the target minimum operating voltage in constant-current regulation. At this time the auxiliary winding can sustain the supply voltage. The output current available to the load to charge the output capacitors is the constant-current regulation target. The equation below assumes the output current of the flyback is available to charge the output capacitance until the minimum output voltage is achieved. C_VDD capacitor is the C3 capacitor in the schematic of Figure 35.

Equation 19.

11.2.1.2.6 VS Resistor Divider

The VS divider resistors determine the output voltage regulation point of the flyback converter, also the high-side divider resistor (R_S1) determines the line voltage at which the controller enables continuous switching operation. R_S1 is initially determined based on transformer auxiliary to primary turn ratio and desired input voltage operating threshold.

Equation 20.

In our example the selected value of R_S1 was 100 kΩ.

The low-side VS pin resistor is selected based on desired output voltage regulation.

Equation 21.

The value selected for R_S2 resistance was 30 kΩ.

11.2.1.2.7 R_VDD Resistor and Turn Ratio

The value of R_VDD and the auxiliary-to-secondary turns ratio should be selected with care in order to be sure that the VDD is always higher than the VDD_OFF (7 V maximum) threshold under all operating conditions. The R_VDD resistor also limits the current that can go into the VDD pin preventing I_{VDDCLP_OC} clamp over-current protection from being erroneously activated.

11.2.1.2.8 Transformer Input Power

The power at the transformer input during full-load condition is given by the output power plus the power loss in the output diode plus the power consumption of the UCC2891x control logic (V_VDD × I_RUN) divided by the transformer efficiency that takes into account all the losses due to the transformer: copper losses, core losses, and energy loss in the leakage inductances.

Equation 22.

11.2.1.2.9 R_IPK Value

The R_IPK value sets the value of the DRAIN current peak that equals the transformer primary winding current peak value. This value also sets the value of the output current when working in CC mode according to the following formula:

Equation 23.

where

• K_CC is the secondary diode conduction duty cycle Electrical Characteristics
• N_PS is the primary-to-secondary transformer turns ratio
• V_CCR is the defined as V_CCR = V_CSTE(max) × K_CC and the value is specified in the Electrical Characteristics

The term takes into account that not all the energy stored in the transformer goes to the secondary side but some of this energy, through the auxiliary winding, is used to supply the device control logic. The transfer of energy always happens with unavoidable losses. These losses are accounted for through the transformer efficiency term (η_XFMR). For a fixed target value for I_OUT, the value of R_IPK can be calculated using the following formula:

Equation 24.

For the example:

Equation 25.

Equation 26.

11.2.1.2.10 Transformer Primary Inductance Value

After you have fixed the maximum switching frequency and the maximum value of the primary current peak for your application, the primary inductance value can be fixed by the following equation:

Equation 27.

L_P_Tol is the tolerance on the primary inductance value of the transformer. Typical values of L_P_Tol are between ±10% and ±15%)

I_{D_PK(max)} is given by:

Equation 28.

For the example:

Equation 29.

11.2.1.2.10.1 Secondary Diode Selection

The maximum reverse voltage that the secondary diode had to sustain can be calculated by the equation below where a margin of 30% is considered. Usually for this kind of application a Schottky diode is used to reduce the power losses due to the lower forward voltage drop. The maximum current rating of the diode is generally selected between two and five times the maximum output current (I_OCC).

Equation 30.

Equation 31.

11.2.1.2.11 Pre-Load

When no load is applied on the converter output, the output voltage rises until the OVP (over voltage protection) of the device is tripped, because the device cannot operate at zero switching frequency. The device's minimum switching frequency of 420 Hz will always deliver some energy to the output, causing the voltage to rise at no load. To avoid this, an R_PRL (pre-load resistance) is used. The value of this pre-load can be selected using the following equation:

Equation 32.

Equation 33.

11.2.1.2.12 DRAIN Voltage Clamp Circuit

The main purpose of this circuit, as in most flyback converters, is to prevent the DRAIN voltage from rising up to the FET break-down voltage, at the FET turn-off, and destroying the FET itself. An additional task, required by the primary-side regulation mechanism, is to provide a clean input to the VS pin by damping the oscillation that is typically present on the DRAIN voltage due to the transformer primary leakage inductance.

To perform damping, the D2 diode (refer to Figure 40) selected should not be a fast recovery diode (0.3 μs < t_rr < 1 μs) so the reverse current can flow in the R_LC over damped circuit. This R_LC circuit is formed by the transformer primary-leakage inductance (L_LKP), the resistance R4, and the capacitance C4. To ensure proper damping the resistance R4 has to satisfy the following condition:

Equation 34.

The capacitance C₄ should not be too high so it does not require too much energy to be charged. Typical values for C₄ are between 100 pF and 1 nF.

The resistance, R5, has been added to discharge the C4 capacitance so at the next switching cycle diode D2 is activated providing enough current and storage to have a reverse-recovery current large enough for proper oscillation damping.

Figure 40. DRAIN Clamp Circuit Options

Table 3. Average Efficiency Performance of the UCC28910FBEVM-526

Table 4. Standby Power, No-Load Power Consumption of the Converter