SLUSCK4C September   2016  – October 2024 UCC28950-Q1 , UCC28951-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Dissipation Ratings
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Start-Up Protection Logic
      2. 6.3.2  Voltage Reference (VREF)
      3. 6.3.3  Error Amplifier (EA+, EA–, COMP)
      4. 6.3.4  Soft-Start and Enable (SS/EN)
      5. 6.3.5  Light-Load Power Saving Features
      6. 6.3.6  Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
      7. 6.3.7  Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
      8. 6.3.8  Minimum Pulse (TMIN)
      9. 6.3.9  Burst Mode
      10. 6.3.10 Switching Frequency Setting
      11. 6.3.11 Slope Compensation (RSUM)
      12. 6.3.12 Dynamic SR ON/OFF Control (DCM Mode)
      13. 6.3.13 Current Sensing (CS)
      14. 6.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
      15. 6.3.15 Synchronization (SYNC)
      16. 6.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
      17. 6.3.17 Supply Voltage (VDD)
      18. 6.3.18 Ground (GND)
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Power Loss Budget
        2. 7.2.2.2  Preliminary Transformer Calculations (T1)
        3. 7.2.2.3  QA, QB, QC, QD FET Selection
        4. 7.2.2.4  Selecting LS
        5. 7.2.2.5  Selecting Diodes DB and DC
        6. 7.2.2.6  Output Inductor Selection (LOUT)
        7. 7.2.2.7  Output Capacitance (COUT)
        8. 7.2.2.8  Select FETs QE and QF
        9. 7.2.2.9  Input Capacitance (CIN)
        10. 7.2.2.10 Current Sense Network (CT, RCS, R7, DA)
          1. 7.2.2.10.1 Voltage Loop Compensation Recommendation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Community Resources
    5. 8.5 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.2 Preliminary Transformer Calculations (T1)

Transformer turns ratio (a1) is:

Equation 23. UCC28950-Q1 UCC28951-Q1

Estimate FET voltage drop (VRDSON) as: VRDSON = 0.3V

Select transformer turns based on 70% duty cycle (DMAX) at minimum specified input voltage. This will give some room for dropout if a PFC front end is used (see Equation 24 and Equation 25).

Equation 24. UCC28950-Q1 UCC28951-Q1
Equation 25. UCC28950-Q1 UCC28951-Q1

Turn the ratio and round is to the nearest whole turn: a1 = 21

Calculate the typical duty cycle (DTYP) based on average input voltage in Equation 26.

Equation 26. UCC28950-Q1 UCC28951-Q1

Output inductor peak-to-peak ripple current is set to 20% of the output current using Equation 27.

Equation 27. UCC28950-Q1 UCC28951-Q1

Take care in selecting the correct amount of magnetizing inductance (LMAG). Equation 28 calculates the minimum magnetizing inductance of the primary of the transformer (T1) to ensure the converter operates in current-mode control. As LMAG reduces, the increasing magnetizing current becomes an increasing proportion of the signal at the CS pin. If the magnetizing current increases enough, it can swamp out the current sense signal across RCS and the converter will operate increasingly as if it were in voltage mode control rather than current mode.

Equation 28. UCC28950-Q1 UCC28951-Q1

Figure 7-4 shows T1 primary current (IPRIMARY) and synchronous rectifiers QE (IQE) and QF (IQF) currents with respect to the synchronous rectifier gate drive currents. IQE and IQF are the same as the secondary winding currents of T1. Variable D is the duty cycle of the converter.

UCC28950-Q1 UCC28951-Q1 T1 Primary and QE and QF FET Currents Figure 7-4 T1 Primary and QE and QF FET Currents

Calculate T1 secondary RMS current (ISRMS) in Equation 29 through Equation 31:

Equation 29. UCC28950-Q1 UCC28951-Q1
Equation 30. UCC28950-Q1 UCC28951-Q1
Equation 31. UCC28950-Q1 UCC28951-Q1

Secondary RMS current (ISRMS1) when energy is being delivered to the secondary (see Equation 32):

Equation 32. UCC28950-Q1 UCC28951-Q1

Secondary RMS current (ISRMS2) when current is circulating through the transformer when QE and QF are both on (see Equation 33).

Equation 33. UCC28950-Q1 UCC28951-Q1

Secondary RMS current (ISRMS3) caused by the negative current in the opposing winding during freewheeling period calculated in Equation 34. Refer to Figure 7-4.

Equation 34. UCC28950-Q1 UCC28951-Q1

Total secondary RMS current (ISRMS) is calculated in Equation 35:

Equation 35. UCC28950-Q1 UCC28951-Q1

Calculate T1 Primary RMS Current (IPRMS) using Equation 36 through Equation 40:

Equation 36. UCC28950-Q1 UCC28951-Q1
Equation 37. UCC28950-Q1 UCC28951-Q1
Equation 38. UCC28950-Q1 UCC28951-Q1
Equation 39. UCC28950-Q1 UCC28951-Q1
Equation 40. UCC28950-Q1 UCC28951-Q1

T1 Primary RMS (IPRMS1) current when energy is being delivered to the secondary (see Equation 41).

Equation 41. UCC28950-Q1 UCC28951-Q1

T1 Primary RMS (IPRMS2) current when the converter is free wheeling. This is calculated in Equation 42:

Equation 42. UCC28950-Q1 UCC28951-Q1

The total T1 primary RMS current (IPRMS) is calculated using Equation 43:

Equation 43. UCC28950-Q1 UCC28951-Q1

For this design, a Vitec™ transformer was selected for part number 75PR8107 with the following specifications:

  • a1 = 21
  • LMAG = 2.8mH
  • measured leakage inductance on the Primary (LLK) is 4µH
  • transformer Primary DC resistance (DCRP) is 0.215Ω
  • transformer Secondary DC resistance (DCRS) is 0.58mΩ
  • estimated transformer core losses (PT1) calculated in Equation 44 are twice the copper loss (which is an estimate and the total losses may vary based on magnetic design)
Equation 44. UCC28950-Q1 UCC28951-Q1

Calculate remaining power budget using Equation 45:

Equation 45. UCC28950-Q1 UCC28951-Q1