SLUSCK4C September   2016  – October 2024 UCC28950-Q1 , UCC28951-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Dissipation Ratings
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Start-Up Protection Logic
      2. 6.3.2  Voltage Reference (VREF)
      3. 6.3.3  Error Amplifier (EA+, EA–, COMP)
      4. 6.3.4  Soft-Start and Enable (SS/EN)
      5. 6.3.5  Light-Load Power Saving Features
      6. 6.3.6  Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
      7. 6.3.7  Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
      8. 6.3.8  Minimum Pulse (TMIN)
      9. 6.3.9  Burst Mode
      10. 6.3.10 Switching Frequency Setting
      11. 6.3.11 Slope Compensation (RSUM)
      12. 6.3.12 Dynamic SR ON/OFF Control (DCM Mode)
      13. 6.3.13 Current Sensing (CS)
      14. 6.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
      15. 6.3.15 Synchronization (SYNC)
      16. 6.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
      17. 6.3.17 Supply Voltage (VDD)
      18. 6.3.18 Ground (GND)
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Power Loss Budget
        2. 7.2.2.2  Preliminary Transformer Calculations (T1)
        3. 7.2.2.3  QA, QB, QC, QD FET Selection
        4. 7.2.2.4  Selecting LS
        5. 7.2.2.5  Selecting Diodes DB and DC
        6. 7.2.2.6  Output Inductor Selection (LOUT)
        7. 7.2.2.7  Output Capacitance (COUT)
        8. 7.2.2.8  Select FETs QE and QF
        9. 7.2.2.9  Input Capacitance (CIN)
        10. 7.2.2.10 Current Sense Network (CT, RCS, R7, DA)
          1. 7.2.2.10.1 Voltage Loop Compensation Recommendation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Community Resources
    5. 8.5 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.11 Slope Compensation (RSUM)

Slope compensation prevents a sub-harmonic oscillation in the controller during in peak current mode (PCM) control operation or during cycle-by-cycle current limit at duty cycles above 50% (some publications suggest it may happen at D < 50%). Slope compensation in the controller adds an additional ramp signal to the CS signal and is applied to:

  • the PWM comparator in the case of peak current mode control
  • the input of the cycle-by-cycle comparator

At low duty cycles and light loads, the slope compensation ramp reduces the noise sensitivity during peak current mode control operation.

Placing a resistor from the RSUM pin to ground allows the controller to operate in PCM control. Connecting a resistor from RSUM to VREF switches the controller to voltage mode control (VMC) with the internal PWM ramp. In VMC the resistor at RSUM provides CS signal slope compensation for operation in cycle-by-cycle current limit. That is, in VMC, the slope compensation is applied only to the cycle-by-cycle comparator while in PCM the slope compensation is applied to both the PWM and cycle-by-cycle current limit comparators. The operation logic of the slope compensation circuit is shown in Figure 6-9.

UCC28950-Q1 UCC28951-Q1 The Operation Logic of Slope Compensation Circuit Figure 6-9 The Operation Logic of Slope Compensation Circuit

Too much slope compensation reduces the benefits of PCM control. In the case of cycle-by-cycle current limit, the average current limit becomes lower and this might reduce the start-up capability into large output capacitances.

The optimum compensation ramp varies, depending on duty cycle, LOUT and LMAG. A good starting point in selecting the amount of slope compensation is to set the slope compensation ramp to be half the inductor current ramp downslope (inductor current ramp during the off time). The inductor current ramp downslope (as seen at the CS pin input, and neglecting the effects of any filtering at the CS pin) is calculated in Equation 12:

Equation 12. m o = V O U T L O U T × R C S a 1 × C T R A T

where

  • VOUT is the output voltage of the converter
  • LOUT is the output inductor value
  • a1 is the transformer turns ratio (NP/NS)
  • CTRAT is the current transformer ratio (IP/IS, typically 100:1)

Selection of LOUT, a1 and CTRAT are described later in this document. The total slope compensation is 0.5m0. Some of this ramp is due to magnetizing current in the transformer, the rest is added by an appropriately chosen resistor from RSUM to ground.

The slope of the additional ramp, me, added to the CS signal by placing a resistor from RSUM to ground is defined by Equation 13.

Equation 13. UCC28950-Q1 UCC28951-Q1

where

  • RSUM is in kΩ
  • me is in V/μs

If the resistor from the RSUM pin is connected to the VREF pin, then the controller operates in voltage mode control, still having the slope compensation ramp added to the CS signal used for cycle-by-cycle current limit. In this case the slope is defined by Equation 14.

Equation 14. UCC28950-Q1 UCC28951-Q1

where

  • VREF is in volts
  • RSUM is in kΩ
  • me is in V/μs

These are empirically derived equations without units agreement. As an example, substituting VREF = 5V and RSUM = 40kΩ, yields the result 0.125V/μs. The related plot of me as a function of RSUM is shown in Figure 6-10, Because VREF = 5V, the plots generated from Equation 13 and Equation 14 coincide.

UCC28950-Q1 UCC28951-Q1 Slope of the Added Ramp Over Resistor RSUM Figure 6-10 Slope of the Added Ramp Over Resistor RSUM
Note:

The recommended resistor range for RSUM is 10kΩ to 1MΩ.