SLUSCK4C September   2016  – October 2024 UCC28950-Q1 , UCC28951-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Dissipation Ratings
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Start-Up Protection Logic
      2. 6.3.2  Voltage Reference (VREF)
      3. 6.3.3  Error Amplifier (EA+, EA–, COMP)
      4. 6.3.4  Soft-Start and Enable (SS/EN)
      5. 6.3.5  Light-Load Power Saving Features
      6. 6.3.6  Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
      7. 6.3.7  Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
      8. 6.3.8  Minimum Pulse (TMIN)
      9. 6.3.9  Burst Mode
      10. 6.3.10 Switching Frequency Setting
      11. 6.3.11 Slope Compensation (RSUM)
      12. 6.3.12 Dynamic SR ON/OFF Control (DCM Mode)
      13. 6.3.13 Current Sensing (CS)
      14. 6.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
      15. 6.3.15 Synchronization (SYNC)
      16. 6.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
      17. 6.3.17 Supply Voltage (VDD)
      18. 6.3.18 Ground (GND)
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Power Loss Budget
        2. 7.2.2.2  Preliminary Transformer Calculations (T1)
        3. 7.2.2.3  QA, QB, QC, QD FET Selection
        4. 7.2.2.4  Selecting LS
        5. 7.2.2.5  Selecting Diodes DB and DC
        6. 7.2.2.6  Output Inductor Selection (LOUT)
        7. 7.2.2.7  Output Capacitance (COUT)
        8. 7.2.2.8  Select FETs QE and QF
        9. 7.2.2.9  Input Capacitance (CIN)
        10. 7.2.2.10 Current Sense Network (CT, RCS, R7, DA)
          1. 7.2.2.10.1 Voltage Loop Compensation Recommendation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Community Resources
    5. 8.5 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Device Functional Modes

The UCC2895x-Q1 controllers offer many operational modes. These modes are described in detail in Section 6.3.

  • Current mode1. The UCC2895x-Q1 controller operates in current mode control when the RSUM pin is connected to GND through a resistor (RSUM) . The resistor sets the amount of slope compensation.
  • Voltage mode1. The controller operates in voltage mode control when the RSUM pin is connected to VREF through a resistor (RSUM). The chosen resistor value gives the correct amount of slope compensation for operation in current limit mode (cycle-by-cycle current limit).
  • DCM mode. The controller enters DCM mode when the signal at the CS pin falls below the level set by the resistor at the DCM pin. The SR drives (OUTE and OUTF) turn off and secondary rectification occurs through the body diodes of the SRs.
  • Burst mode. The controllers enter burst mode when the pulse width demanded by the feedback signal falls below the width set by the resistor at the TMIN pin.
  • Leader mode. This is the default operation mode of the controller and is used when there is only one UCC2895x-Q1 controller in the system. Connect the timing resistor (RT) from the RT pin to VREF. In a system with more than one UCC2895x-Q1 controller, configure one as the leader and the others as followers1.
  • Follower mode. The follower controller operates with a 90° phase shift relative to the leader (providing their SYNC pins are tied together). Connect the timing resistor (RT) from the RT pin to GND and connect an 825kΩ ±5% resistor from the SS/EN pin to GND1.
  • Synchronized mode. When a UCC2895x-Q1 controller is configured as a follower, its SYNC pin is used as an input. The follower synchronizes its internal oscillator at 90° to the signal at its SYNC pin. The application note, Synchronizing Three or More UCC28950 Phase-Shifted, Full-Bridge Controllers, discusses how multiple follower controllers may be synchronized to a single leader oscillator.
  • Hiccup mode. This mode provides overload protection to the power circuit. The UCC2895x-Q1 controller stops switching after a certain time in current limit. It starts again (soft-start) after a delay time. The user can control the time spent in current limit before switching is stopped and the delay time before the soft start happens.
  • Current-limit mode. The UCC2895x-Q1c ontroller provides cycle-by-cycle current limiting when the signal at the CS pin reaches 2V.
  • Latch-off mode. Connect a resistor between the SS pin and VREF. The UCC2895x-Q1 controller then latches off when the controller enterscurrent-limit mode. (1)
1. Current mode control and voltage mode control are mutually exclusive as are leader and follower modes.