SLUSCK4C September   2016  – October 2024 UCC28950-Q1 , UCC28951-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Dissipation Ratings
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Start-Up Protection Logic
      2. 6.3.2  Voltage Reference (VREF)
      3. 6.3.3  Error Amplifier (EA+, EA–, COMP)
      4. 6.3.4  Soft-Start and Enable (SS/EN)
      5. 6.3.5  Light-Load Power Saving Features
      6. 6.3.6  Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
      7. 6.3.7  Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
      8. 6.3.8  Minimum Pulse (TMIN)
      9. 6.3.9  Burst Mode
      10. 6.3.10 Switching Frequency Setting
      11. 6.3.11 Slope Compensation (RSUM)
      12. 6.3.12 Dynamic SR ON/OFF Control (DCM Mode)
      13. 6.3.13 Current Sensing (CS)
      14. 6.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
      15. 6.3.15 Synchronization (SYNC)
      16. 6.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
      17. 6.3.17 Supply Voltage (VDD)
      18. 6.3.18 Ground (GND)
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Power Loss Budget
        2. 7.2.2.2  Preliminary Transformer Calculations (T1)
        3. 7.2.2.3  QA, QB, QC, QD FET Selection
        4. 7.2.2.4  Selecting LS
        5. 7.2.2.5  Selecting Diodes DB and DC
        6. 7.2.2.6  Output Inductor Selection (LOUT)
        7. 7.2.2.7  Output Capacitance (COUT)
        8. 7.2.2.8  Select FETs QE and QF
        9. 7.2.2.9  Input Capacitance (CIN)
        10. 7.2.2.10 Current Sense Network (CT, RCS, R7, DA)
          1. 7.2.2.10.1 Voltage Loop Compensation Recommendation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Community Resources
    5. 8.5 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.9 Input Capacitance (CIN)

The input voltage in this design is 390VDC, which is typically fed by the output of a PFC boost pre-regulator. It is typical to select input capacitance based on holdup and ripple requirements.

Note:

The delay time needed to achieve ZVS can act as a duty cycle clamp (DCLAMP).

Calculate tank frequency using Equation 89:

Equation 89. UCC28950-Q1 UCC28951-Q1

Estimate the delay time using Equation 90:

Equation 90. UCC28950-Q1 UCC28951-Q1

The effective duty cycle clamp (DCLAMP) is calculated in Equation 91:

Equation 91. UCC28950-Q1 UCC28951-Q1

VDROP is the minimum input voltage where the converter can still maintain output regulation (see Equation 92). The converter’s input voltage would only drop down this low during a brownout or line-drop condition if this converter was following a PFC pre-regulator.

Equation 92. UCC28950-Q1 UCC28951-Q1

CIN was calculated in Equation 93 based on one line cycle of holdup:

Equation 93. UCC28950-Q1 UCC28951-Q1

Calculate the high-frequency input capacitor RMS current (ICINRMS) using Equation 94.

Equation 94. I C I N R M S = I P R M S 1 2 - P O U T V V I N m i n ×   η = 1.8   A

To meet the input capacitance and RMS current requirements for this design, a 330µF capacitor was chosen from Panasonic part number EETHC2W331EA:

CIN = 330µF

This capacitor has a high frequency (ESRCIN) of 150mΩ and is measured with an impedance analyzer at 200kHz. ESRCIN = 0.150Ω

Estimate the CIN power dissipation (PCIN) using Equation 95:

Equation 95. UCC28950-Q1 UCC28951-Q1

And recalculate the remaining power budget using Equation 96:

Equation 96. UCC28950-Q1 UCC28951-Q1

There is approximately 6.0W that remains in the power budget for the current-sensing network, to bias the control device, and for all resistors supporting the control device.