SLUSDB2B August   2018  – October 2024 UCC28950 , UCC28951

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Dissipation Ratings
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Start-Up Protection Logic
      2. 6.3.2  Voltage Reference (VREF)
      3. 6.3.3  Error Amplifier (EA+, EA–, COMP)
      4. 6.3.4  Soft-Start and Enable (SS/EN)
      5. 6.3.5  Light-Load Power Saving Features
      6. 6.3.6  Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
      7. 6.3.7  Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
      8. 6.3.8  Minimum Pulse (TMIN)
      9. 6.3.9  Burst Mode
      10. 6.3.10 Switching Frequency Setting
      11. 6.3.11 Slope Compensation (RSUM)
      12. 6.3.12 Dynamic SR ON/OFF Control (DCM Mode)
      13. 6.3.13 Current Sensing (CS)
      14. 6.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
      15. 6.3.15 Synchronization (SYNC)
      16. 6.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
      17. 6.3.17 Supply Voltage (VDD)
      18. 6.3.18 Ground (GND)
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Power Loss Budget
        2. 7.2.2.2  Preliminary Transformer Calculations (T1)
        3. 7.2.2.3  QA, QB, QC, QD FET Selection
        4. 7.2.2.4  Selecting LS
        5. 7.2.2.5  Selecting Diodes DB and DC
        6. 7.2.2.6  Output Inductor Selection (LOUT)
        7. 7.2.2.7  Output Capacitance (COUT)
        8. 7.2.2.8  Select FETs QE and QF
        9. 7.2.2.9  Input Capacitance (CIN)
        10. 7.2.2.10 Current Sense Network (CT, RCS, R7, DA)
          1. 7.2.2.10.1 Voltage Loop Compensation Recommendation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Community Resources
    5. 8.5 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.6 Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))

The resistor RAB from the DELAB pin, DELAB to GND, along with the resistor divider RAHI from CS pin to ADEL pin and RA from ADEL pin to GND sets the delay TABSET between one of outputs OUTA or OUTB going low and the other output going high Figure 6-1. The total resistance of this resistor divider should be in the range between 10kΩ and 20kΩ

UCC28950 UCC28951 Delay Definitions Between OUTA and OUTB, OUTC and OUTDFigure 6-1 Delay Definitions Between OUTA and OUTB, OUTC and OUTD

This delay gradually increases as a function of the CS signal from TABSET1, which is measured at VCS = 1.8V, to TABSET2, which is measured at the VCS = 0.2V. This approach ensures there will be no shoot-through current during the high-side and low-side MOSFET switching and optimizes the delay for acheiving ZVS condition over a wide load current range. The ratio between the longest and shortest delays is set by the resistor divider RAHI and RA. The maximum ratio is achieved by tying the CS and ADEL pins together. If ADEL is connected to GND, then the delay is fixed, defined only by the resistor RAB from DELAB to GND. The delay TCDSET1 and TCDSET2 settings and their behaviour for outputs OUTC and OUTD are very similar to the one described for OUTA and OUTB. The difference is that resistor RCD connected between DELCD pin and GND sets the delay TCDSET. The ratio between the longest and shortest delays is set by the resistor divider RAHI and RA.

The delay time TABSET is defined by the following Equation 3 .

Equation 3. TABSET=RAB×5VCS×KA×0.927+0.22V×1pF-12.6ns

where

  • the CS, which is the voltage at pin CS, is in volts
  • KA is a numerical gain factor of CS voltage from 0 to 1

The same equation is used to define the delay time TCDSET in another leg, except RAB is replaced by RCD (see Equation 4).

Equation 4. TCDSET=RCD×5VCS×KA×0.927+0.22V×1pF-12.6ns

where

  • the CS, which is the voltage at pin CS, is in volts
  • KA is a numerical gain factor of CS voltage from 0 to 1

These equations are empirical and they are approximated from measured data. Thus, there is no unit agreement in the equations. As an example, assume RAB = 15kΩ, CS = 1V and KA = 0.5. Then the TABSET is approximately 90ns.

In Equation 5, KA is the same and is defined as Equation 5:

Equation 5. UCC28950 UCC28951

KA sets how the delay varies with the CS pin voltage as shown in Figure 6-2 and Figure 6-3.

TI recommends starting by setting KA = 0 and set TABSET and TCDSET relatively large using equations or plots in this data sheet to avoid hard switching or even shoot through current. The delay between outputs A, B and C, D set by resistors RAB and RCD accordingly. Program the optimal delays at light load first. Then by changing KA set the optimal delay for the outputs A, B at maximum current. KA for outputs C, D is the same as for A, B. Usually outputs C, D always have ZVS if sufficient delay is provided.

Note:

The allowed resistor range on DELAB and DELCD, RAB and RCD is 13kΩ to 90kΩ.

RA and RAHI define the portion of voltage at pin CS applied to the pin ADEL (see Figure 7-3). KA defines how significantly the delay time depends on CS voltage. KA varies from 0, where ADEL pin is shorted to ground (RA = 0) and the delay does not depend on CS voltage, to 1, where ADEL is tied to CS (RAHI = 0). Setting KA, RAB, and RCD provides the ability to maintain optimal ZVS conditions of primary switches over load current because the voltage at CS pin includes the load current reflected to the primary side through the current-sensing circuit. The plots in Figure 6-2 and Figure 6-3 show the delay time settings as a function of CS voltage and KA for two different conditions: RAB = RCD = 13kΩ (Figure 6-2) and RAB = RCD = 90kΩ (Figure 6-3).

UCC28950 UCC28951 Delay Time Set TABSET and TCDSET (Over CS Voltage Variation and selected KA for RAB and RCD Equal 13kΩ)Figure 6-2 Delay Time Set TABSET and TCDSET (Over CS Voltage Variation and selected KA for RAB and RCD Equal 13kΩ)
UCC28950 UCC28951 Delay Time set TABSET and TCDSET (Over CS Voltage Variation and Selected KA for RAB and RCD Equal 90 kΩ)Figure 6-3 Delay Time set TABSET and TCDSET (Over CS Voltage Variation and Selected KA for RAB and RCD Equal 90 kΩ)