SLUSDB2B August   2018  – October 2024 UCC28950 , UCC28951

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Dissipation Ratings
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Start-Up Protection Logic
      2. 6.3.2  Voltage Reference (VREF)
      3. 6.3.3  Error Amplifier (EA+, EA–, COMP)
      4. 6.3.4  Soft-Start and Enable (SS/EN)
      5. 6.3.5  Light-Load Power Saving Features
      6. 6.3.6  Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
      7. 6.3.7  Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
      8. 6.3.8  Minimum Pulse (TMIN)
      9. 6.3.9  Burst Mode
      10. 6.3.10 Switching Frequency Setting
      11. 6.3.11 Slope Compensation (RSUM)
      12. 6.3.12 Dynamic SR ON/OFF Control (DCM Mode)
      13. 6.3.13 Current Sensing (CS)
      14. 6.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
      15. 6.3.15 Synchronization (SYNC)
      16. 6.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
      17. 6.3.17 Supply Voltage (VDD)
      18. 6.3.18 Ground (GND)
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Power Loss Budget
        2. 7.2.2.2  Preliminary Transformer Calculations (T1)
        3. 7.2.2.3  QA, QB, QC, QD FET Selection
        4. 7.2.2.4  Selecting LS
        5. 7.2.2.5  Selecting Diodes DB and DC
        6. 7.2.2.6  Output Inductor Selection (LOUT)
        7. 7.2.2.7  Output Capacitance (COUT)
        8. 7.2.2.8  Select FETs QE and QF
        9. 7.2.2.9  Input Capacitance (CIN)
        10. 7.2.2.10 Current Sense Network (CT, RCS, R7, DA)
          1. 7.2.2.10.1 Voltage Loop Compensation Recommendation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Community Resources
    5. 8.5 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.10 Current Sense Network (CT, RCS, R7, DA)

The CT chosen for this design has a turns ratio (CTRAT) of 100:1 in Equation 97:

Equation 97. UCC28950 UCC28951

Calculate nominal peak current (IP1) at VINMIN:

The peak primary current is calculated using Equation 98:

Equation 98. UCC28950 UCC28951

The CS pin voltage where peak current limit will trip is:

Equation 99. UCC28950 UCC28951

Calculate current sense resistor (RCS) and leave 300mV for slope compensation using Equation 100. Include a 1.1 factor for margin:

Equation 100. UCC28950 UCC28951

Select a standard resistor for RCS:

Equation 101. UCC28950 UCC28951

Estimate the power loss for RCS using Equation 102:

Equation 102. UCC28950 UCC28951

Calculate maximum reverse voltage (VDA) on DA using Equation 103:

Equation 103. UCC28950 UCC28951

Estimate the DA power loss (PDA) using Equation 104:

Equation 104. UCC28950 UCC28951

Calculate reset resistor R7:

Resistor R7 is used to reset the current sense transformer CT:

Equation 105. UCC28950 UCC28951

Resistor RLF1 and capacitor CLF form a low-pass filter for the current sense signal (Pin 15). For this design, chose the following values. This filter has a low frequency pole (fLFP) at 482kHz, (which is appropriate for most applications) but may be adjusted to suit individual layouts and EMI present in the design.

Equation 106. UCC28950 UCC28951
Equation 107. UCC28950 UCC28951
Equation 108. UCC28950 UCC28951

The UCC2895x VREF output (Pin 1) needs a high frequency bypass capacitor to filter out high frequency noise. This pin needs at least 1µF of high-frequency bypass capacitance (CREF).

Equation 109. UCC28950 UCC28951

The voltage amplifier reference voltage (Pin 2, EA +) can be set with a voltage divider (R1, R2), for this design example, the error amplifier reference voltage (V1) will be set to 2.5V. Select a standard resistor value for R1 and then calculate resistor value R2.

UCC2895x reference voltage:

Equation 110. UCC28950 UCC28951

Set voltage amplifier reference voltage:

Equation 111. UCC28950 UCC28951
Equation 112. UCC28950 UCC28951
Equation 113. UCC28950 UCC28951

The voltage divider formed by resistor R3 and R4 are chosen to set the DC output voltage (VOUT) at Pin 3 (EA-).

Select a standard resistor for R3:

Equation 114. UCC28950 UCC28951

Calculate R4 using Equation 115:

Equation 115. UCC28950 UCC28951

Then choose a standard resistor for R4 using Equation 116:

Equation 116. UCC28950 UCC28951
Note:

TI recommends using an RCD clamp to protect the output synchronous FETs from overvoltage due to switch node ringing.

UCC28950 UCC28951 Daughter Board Schematic Figure 7-5 Daughter Board Schematic