SLUS458I July 2000 – June 2024 UCC28C40 , UCC28C41 , UCC28C42 , UCC28C43 , UCC28C44 , UCC28C45 , UCC38C40 , UCC38C41 , UCC38C42 , UCC38C43 , UCC38C44 , UCC38C45
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The soft-start timing is the technique to gradually power up the converter in a well-controlled fashion by slowly increasing the effective duty cycle starting at zero and gradually rising. Following start-up of the PWM, the error amplifier inverting input is low, commanding the error amplifier’s output to go high. The output stage of the amplifier can source 1mA typically, which is enough to drive most high impedance compensation networks, but not enough for driving large loads quickly. Soft-start timing is achieved by charging a fairly large value, >1µF, capacitor (CSS) connected to the error amplifier output through a PNP transistor as shown in Figure 7-6
The limited charging current of the amplifier into the capacitor translates into a dv/dt limitation on the error amplifier output. This directly corresponds to some maximum rate of change of primary current in a current mode controlled system as one of the PWM comparator inputs gradually rises. The values of RSS and CSS must be selected to bring the COMP pin up at a controlled rate, limiting the peak current supplied by the power stage. After the soft-start interval is complete, the capacitor continues to charge to VREF, effectively removing the PNP transistor from the circuit consideration. Soft-start timing offers a different, frequently preferred function in current mode controlled systems than it does in voltage mode control. In current mode, soft start controls the rising of the peak switch current. In voltage mode control, soft start gradually widens the duty cycle, regardless of the primary current or rate of ramp-up.
The purpose of resistor RSS and the diode is to remove the soft-start capacitor from the error amplifier path during normal operation, after the soft-start period completes and the capacitor charges fully. The optional diode in parallel with the resistor forces a soft-start period each time the PWM goes through UVLO condition that forces VREF to go low. Without the diode, the capacitor remains charged during a brief loss of supply or brown-out, and the device does not emable a soft-start function upon re-application of VDD.