The UCC33410
integrated isolated power solution simplifies
system design and reduces board area usage. Proper
PCB layout is important in order to achieve
optimum performance. Here is a list of
recommendations:
- Place decoupling
capacitors as close as possible to the device pins. For the input supply, place
0402 and 0805 ceramic capacitor between pin 2 (VINP) and pins 3, 4, 5 and 6
(GNDP). For the isolated output supply, place 0402 and 0805 ceramaic capacitora
between pin 8 (VCC) and pins 9, 10, 11 and 12 (GNDS). This location is of
particular importance to the input decoupling capacitor, because this capacitor
supplies the transient current associated with the fast switching waveforms of
the power drive circuits.
- Because the device does not have a thermal pad
for heat-sinking, the device dissipates heat
through the respective GND pins. Ensure that
enough copper (preferably a connection to the
ground plane) is present on all GNDP and GNDS pins
for best heat-sinking. Placing vias close to the
device pins and away from the high frequency path
between the ceramic capacitors and the device pins
is essential for better thermal performance.
- If space and layer count allow, it is also
recommended to connect the VINP, GNDP, VCC and
GNDS pins to internal ground or power planes
through multiple vias of adequate size.
Alternatively, make traces for these nets as wide
as possible to minimize losses.
- Pay close attention to the
spacing between primary ground plane (GNDP) and secondary ground plane (GNDS) on
the PCB outer layers. The effective creepage and or clearance of the system
reduces if the two ground planes have a lower spacing than that of the device
package.
- To ensure isolation performance between the
primary and secondary side, avoid placing any PCB
traces or copper below the UCC33410 device on the outer copper
layers.