SLUSDR3B June   2019  – February 2024 UCC5390-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Function
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications for DWV Package
    7. 5.7  Safety-Related Certifications For DWV Package
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 6.1.1 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supply
      2. 7.3.2 Input Stage
      3. 7.3.3 Output Stage
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Undervoltage Lockout (UVLO)
        2. 7.3.4.2 Active Pulldown
        3. 7.3.4.3 Short-Circuit Clamping
    4. 7.4 Device Functional Modes
      1. 7.4.1 ESD Structure
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing IN+ and IN– Input Filter
        2. 8.2.2.2 Gate-Driver Output Resistor
        3. 8.2.2.3 Estimate Gate-Driver Power Loss
        4. 8.2.2.4 Estimating Junction Temperature
      3. 8.2.3 Selecting VCC1 and VCC2 Capacitors
        1. 8.2.3.1 Selecting a VCC1 Capacitor
        2. 8.2.3.2 Selecting a VCC2 Capacitor
        3. 8.2.3.3 Application Circuits With Output Stage Negative Bias
      4. 8.2.4 Application Curve
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 PCB Material
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Certifications
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.4 Estimating Junction Temperature

Use the equation below to estimate the junction temperature (TJ) of the UCC5390-Q1 family.

Equation 12. GUID-3A497B0D-87D9-4907-861A-78A9DA006A3D-low.gif

where

  • TC is the UCC5390-Q1 case-top temperature measured with a thermocouple or some other instrument.
  • ΨJT is the junction-to-top characterization parameter from the Thermal Information table.

Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance (RθJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the total energy is released through the top of the case (where thermocouple measurements are usually conducted). The RθJC resistance can only be used effectively when most of the thermal energy is released through the case, such as with metal packages or when a heat sink is applied to an IC package. In all other cases, use of RθJC will inaccurately estimate the true junction temperature. The ΨJT parameter is experimentally derived by assuming that the dominant energy leaving through the top of the IC will be similar in both the testing environment and the application environment. As long as the recommended layout guidelines are observed, junction temperature estimations can be made accurately to within a few degrees Celsius.