SLUSFL3B June   2024  – October 2024 UCC57102 , UCC57108

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stage
      2. 6.3.2 Enable Function
      3. 6.3.3 Driver Stage
      4. 6.3.4 Desaturation (DESAT) Protection
      5. 6.3.5 Fault (FLT)
      6. 6.3.6 VREF
      7. 6.3.7 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7  Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VDD Undervoltage Lockout
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

VDD = 15 V, VEE = 0 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VEE to GND, TJ = –40°C to +150°C, CL = 0 pF, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IVDDQ VDD quiescent supply current VIN = 3.3V, EN = 5V, VDD = 6.5V 1.4 mA
IVDD VDD static supply current VIN = 3.3 V, EN = 5V 1.1 1.5 mA
IVDD VDD static supply current VIN = 0 V, EN = 5V 0.8 1.2 mA
IVEEQ VEE static supply current VIN = 0 V, EN = 5V, VEE = -10V 1.1 mA
IVDDO VDD dynamic operating current fSW = 1 MHz, EN = 5V, VDD=15 V, CL=1.8nF 35 mA
IDIS VDD disable current VIN = 3.3 V, EN = 0 V 0.8 1.1 mA
VDD UNDERVOLTAGE THRESHOLDS AND DELAY
VVDD_ON VDD UVLO Rising Threshold 8-V UVLO Option 7.6 8 8.4 V
VVDD_OFF VDD UVLO Falling Threshold 8-V UVLO Option 6.65 7 7.35 V
VVDD_HYS VDD UVLO Threshold Hysteresis 8-V UVLO Option 1 V
tUVLO2FLT Propagation delay from UVLO shutdown to FLT 8.4 us
VVDD_ON VDD UVLO Rising Threshold 12.5-V UVLO Option 12.8 13.5 14.2 V
VVDD_OFF VDD UVLO Falling Threshold 12.5-V UVLO Option 11.8 12.5 13.2 V
VVDD_HYS VDD UVLO Threshold Hysteresis 12.5-V UVLO Option 1.0 V
VREF
VREF Voltage Reference IREF=10mA 5 V
IREF Reference output current 20 mA
IN, EN
VINH Input High Threshold Voltage 1.8 2.2 2.6 V
VINL Input Low Threshold Voltage 0.8 1.2 1.6 V
VIN_HYS Input-threshold Hysteresis 1.0 V
RIND IN Pin Pull Down Resistance IN=EN= 3.3V 120 kΩ
VENH Enable High Threshold Voltage 1.8 2.2 2.6 V
VENL Enable Low Threshold Voltage 0.8 1.2 1.6 V
VEN_HYS Enable Threshold Hysteresis 1 V
RENU EN Pin Pull Up Resistance EN = 0V 400 kΩ
VFLTth FLT threshold voltage IFLT-sink = 15mA 0.43 1 V
DESAT DETECTION
ICHG Blanking capacitor charge current VDESAT = 3.25V 200 250 316
µA
IDCHG DESAT pin discharge current VDESAT = 8V -20 mA
VDESATTH DESAT Detection Threshold 6.0 6.5 7.0 V
VDESLO DESAT voltage when OUT=L, referenced to GND 100 mV
tDESLEB1 (1) Leading edge blanking time 150 ns
tDESFIL(1) DESAT deglitch filter 100 150 ns
tDES2OUT(1) DESAT propagation delay to 90% of OUT VDESAT>VDESATTH 140 250 ns
tDES2FLT(1) DESAT propagation delay to FLT low VDESATTH to 90% of FLT  135 250 ns
SOFT TURN OFF
RSTO Internal Soft turn-off Pulldown Resistance DESAT triggered, VOUT=5V 35 Ω
OVERTEMPERATURE PROTECTION
TSD(1) Overtemperature threshold 180 C
THYS(1) Overtemperature protection hysteresis 30 C
tOTP2FLT(1) Propagation delay from overtemperature shutdown to FLT Over temperature shutdow to 90% of FLT  8 us
OUTPUT DRIVER STAGE
ISRCPK(1) Peak Output Source Current CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz -3 A
ISNKPK(1) Peak Output Sink Current CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz 3 A
ROH Pull up resistance IOUT = –500mA 5 Ω
ROL Pull down resistance IOUT = 500mA 1 Ω
(1) Parameters are not tested in production.