SLUSCA5B December   2015  – January 2017 UCD3138064A

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Options
    1. 3.1 Device Comparison Table
  4. 4Pin Configuration and Functions
    1. 4.1 Pin Diagrams
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 PMBus/SMBus/I2C Timing
    8. 5.8 Parametric Measurement Information
    9. 5.9 Typical Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 ARM Processor
    3. 6.3 Memory
    4. 6.4 Feature Description
      1. 6.4.1  System Module
        1. 6.4.1.1 Address Decoder (DEC)
        2. 6.4.1.2 Memory Management Controller (MMC)
        3. 6.4.1.3 System Management (SYS)
        4. 6.4.1.4 Central Interrupt Module (CIM)
      2. 6.4.2  Peripherals
        1. 6.4.2.1 Digital Power Peripherals
          1. 6.4.2.1.1 Front End
          2. 6.4.2.1.2 DPWM Module
          3. 6.4.2.1.3 DPWM Events
          4. 6.4.2.1.4 High Resolution DPWM
          5. 6.4.2.1.5 Over Sampling
          6. 6.4.2.1.6 DPWM Interrupt Generation
          7. 6.4.2.1.7 DPWM Interrupt Scaling/Range
      3. 6.4.3  Synchronous Rectifier Dead Time Optimization Peripheral
      4. 6.4.4  Automatic Mode Switching
        1. 6.4.4.1 Phase Shifted Full Bridge Example
        2. 6.4.4.2 LLC Example
        3. 6.4.4.3 Mechanism For Automatic Mode Switching
      5. 6.4.5  DPWMC, Edge Generation, IntraMux
      6. 6.4.6  Filter
        1. 6.4.6.1 Loop Multiplexer
        2. 6.4.6.2 Fault Multiplexer
      7. 6.4.7  Communication Ports
        1. 6.4.7.1 SCI (UART) Serial Communication Interface
        2. 6.4.7.2 PMBUS/I2C
        3. 6.4.7.3 SPI
      8. 6.4.8  Timers
        1. 6.4.8.1 24-Bit Timer
        2. 6.4.8.2 16-Bit PWM Timers
        3. 6.4.8.3 Watchdog Timer
      9. 6.4.9  General Purpose ADC12
      10. 6.4.10 Miscellaneous Analog
      11. 6.4.11 Brownout
      12. 6.4.12 Global I/O
      13. 6.4.13 Temperature Sensor Control
      14. 6.4.14 I/O Mux Control
      15. 6.4.15 Current Sharing Control
      16. 6.4.16 Temperature Reference
    5. 6.5 Device Functional Modes
      1. 6.5.1 DPWM Modes Of Operation
        1. 6.5.1.1 Normal Mode
        2. 6.5.1.2 Phase Shifting
        3. 6.5.1.3 DPWM Multiple Output Mode
        4. 6.5.1.4 DPWM Resonant Mode
      2. 6.5.2 Triangular Mode
      3. 6.5.3 Leading Edge Mode
    6. 6.6 Memory
      1. 6.6.1 Register Maps
        1. 6.6.1.1 CPU Memory Map and Interrupts
          1. 6.6.1.1.1 Memory Map (After Reset Operation)
          2. 6.6.1.1.2 Memory Map (Normal Operation)
          3. 6.6.1.1.3 Memory Map (System and Peripherals Blocks)
        2. 6.6.1.2 Boot ROM
        3. 6.6.1.3 Customer Boot Program
        4. 6.6.1.4 Flash Management
        5. 6.6.1.5 Synchronous Rectifier MOSFET Ramp and IDE Calculation
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration Overview
        2. 7.2.2.2 DPWM Initialization for PSFB
          1. 7.2.2.2.1 DPWM Synchronization
        3. 7.2.2.3 Fixed Signals to Bridge
        4. 7.2.2.4 Dynamic Signals to Bridge
        5. 7.2.2.5 System Initialization for PCM
          1. 7.2.2.5.1 Use of Front Ends and Filters in PSFB
          2. 7.2.2.5.2 Peak Current Detection
          3. 7.2.2.5.3 Peak Current Mode (PCM)
      3. 7.2.3 Application Curves
      4. 7.2.4 Power Supply Recommendations
      5. 7.2.5 Layout
        1. 7.2.5.1 Device Grounding and Layout Guidelines
        2. 7.2.5.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Community Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Device Options

3.1 Device Comparison Table

FEATURE UCD
3138
3138A
RHA/RMH 		3138
3138A
RGC		 3138064
3138064A
RGC 		3138064
RGZ		 3138128
3138128A
PFC		 3138A64
3138A64A
PFC
Package Offering 40 Pin QFN
(6 mm x 6 mm)		 64 Pin QFN
(9 mm x 9 mm)		 64 Pin QFN
(9 mm x 9 mm)		 48 Pin QFN
(7 mm x 7 mm)		 80 Pin QFP
(14 mm x 14 mm)
(Includes leads)		 80 Pin QFP
(14 mm x 14 mm)
(Includes leads)
ARM7TDMI-S Core Processor 31.25 MHz 31.25 MHz 31.25 MHz 31.25 MHz 31.25 MHz 31.25 MHz
High Resolution DPWM Outputs (250ps Resolution) 8 8 8 8 8 8
Number of High Speed Independent Feedback Loops (# Regulated Output Voltages 3 3 3 3 3 3
12-bit, 256kps, General Purpose ADC Channels 7 14 14 9 15 15
Digital Comparators at ADC Outputs 4 4 4 4 4 4
Flash Memory (Program) 32 kB 32 kB 64 kB 64 kB 128 kB 64 kB
Number of Memory 32kB Flash Memory Banks 1 1 2 2 4 Only 1 bank of 64 kB Flash available
Flash Memory (Data) 2 kB 2 kB 2 kB 2 kB 2 kB 2 kB
RAM 4 kB 4 kB 4 kB 4 kB 8 kB 8 kB
Programmable Fault Inputs 1 + 2(1) 4 2 + 2(1) 1 + 2(1) 4 4
High Speed Analog Comparators with Cycle-by-Cycle Current Limiting 6 7 7 6 7 7
UART (SCI) 1(1) 2 2 2 2 2
PMBus/I2C 1 1 1 1 1 1
Additional I2C 0 0 1(1) 1(1) 1 1
SPI 0 0 1(1) 1(1) 1 1
Timers 4 (16 bit) and
1 (24 bit)		 4 (16 bit) and
1 (24 bit)		 4 (16 bit) and
1 (24 bit)		 4 (16 bit) and
1 (24 bit)		 4 (16 bit) and
2 (24 bit)		 4 (16 bit) and
2 (24 bit)
Timer PWM Outputs 1(1) 2 2 1(1) 4 4
Timer Capture Inputs 2(1) 1 + 3(1) 1 + 3(1) 2(1) 2 + 2(1) 2 + 2(1)
Total Digital GPIOs 18 30 30 24 43 43
External Interrupts 0 1 1 0 1 1
External Crystal Clock Support no no no no Yes (pins #61, 62) Yes (pins #61, 62)
Peak Current Mode Control EADC2 Only EADC Only All EADC channels All EADC channels All EADC Channels All EADC Channels
(1) Represents an alternate pin out that is programmable via firmware.