SLUSBZ8B
June 2014 – February 2017
UCD3138128
,
UCD3138A64
PRODUCTION DATA.
1
Features
2
Applications
3
Revision History
4
Description
5
Product Family Comparison
6
Product Feature Overview
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
Handling Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing Characteristics
8.7
PMBUS/SMBUS/IC Timing2
8.8
Timing Requirements
8.9
Power On Reset (POR) / Brown Out Detect (BOD)
8.10
Typical Clock Gating Power Savings
8.11
Typical Characteristics
9
Detailed Description
9.1
Overview
9.1.1
ARM Processor
9.1.2
Memory
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
System Module
9.3.1.1
Address Decoder (DEC)
9.3.1.2
Memory Management Controller (MMC)
9.3.1.3
System Management (SYS)
9.3.1.4
Central Interrupt Module (CIM)
9.3.2
Peripherals
9.3.2.1
Digital Power Peripherals
9.3.2.1.1
Front End
9.3.2.1.2
DPWM Module
9.3.2.1.3
DPWM Events
9.3.2.1.4
High Resolution DPWM
9.3.2.1.5
Over Sampling
9.3.2.1.6
DPWM Interrupt Generation
9.3.2.1.7
DPWM Interrupt Scaling/Range
9.3.3
Automatic Mode Switching
9.3.3.1
Phase Shifted Full Bridge Example
9.3.3.2
LLC Example
9.3.3.3
Mechanism For Automatic Mode Switching
9.3.4
DPWMC, Edge Generation, Intramux
9.3.5
Filter
9.3.5.1
Loop Multiplexer
9.3.5.2
Fault Multiplexer
9.3.6
Communication Ports
9.3.6.1
SCI (UART) Serial Communication Interface
9.3.6.2
PMBUS/I2C
9.3.6.3
SPI
9.3.7
Real Time Clock
9.3.8
Timers
9.3.8.1
24-Bit Timer
9.3.8.2
16-Bit PWM Timers
9.3.8.3
Watchdog Timer
9.3.9
General Purpose ADC12
9.3.10
Miscellaneous Analog
9.3.11
Brownout
9.3.12
Global I/O
9.3.13
Temperature Sensor Control
9.3.14
I/O Mux Control
9.3.15
Current Sharing Control
9.3.16
Temperature Reference
9.4
Device Functional Modes
9.4.1
DPWM Modes Of Operation
9.4.1.1
Normal Mode
9.4.1.2
Phase Shifting
9.4.1.3
DPWM Multiple Output Mode
9.4.1.4
DPWM Resonant Mode
9.4.2
Triangular Mode
9.4.3
Leading Edge Mode
9.5
Register Maps
9.5.1
CPU Memory Map And Interrupts
9.5.1.1
Memory Map (After Reset Operation)
9.5.1.2
Memory Map (Normal Operation)
9.5.1.3
Memory Map (System And Peripherals Blocks)
9.5.2
Boot ROM
9.5.3
Customer Boot Program
9.5.4
Flash Management
9.6
Synchronous Rectifier MOSFET Ramp And IDE Calculation
10
Applications and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration Overview
10.2.2.2
DPWM Initialization for PSFB
10.2.2.3
DPWM Synchronization
10.2.2.4
Fixed Signals to Bridge
10.2.2.5
Dynamic Signals to Bridge
10.2.3
System Initialization for PCM
10.2.3.1
Use of Front Ends and Filters in PSFB
10.2.3.2
Peak Current Detection
10.2.3.3
Peak Current Mode (PCM)
10.2.4
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Device Grounding and Layout Guidelines
12.2
Layout Examples
13
Device and Documentation Support
13.1
Device Support
13.1.1
Development Support
13.2
Documentation Support
13.2.1
Related Links
13.2.2
Related Documentation
13.2.2.1
References
13.3
Trademarks
13.4
Electrostatic Discharge Caution
13.5
Glossary
14
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PFC|80
MTQF009B
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slusbz8b_oa
slusbz8b_pm
11
Power Supply Recommendations
Both 3.3 VD and 3.3 VA should have a local 4.7 µF capacitor placed as close as possible to the device pins
BP18 should have a 1 µF capacitor.