8.3.1 Body-Diode Conduction Detection

In Figure 24, V_DS is the drain-to-source voltage which is connected to the VD pin. The IN pin is the gate-driver input-command signal from the UCD3138A digital controller. The DTC pin is the sensed body-diode conduction. The OUT pin is the gate-driver output. The body-diode conduction detection comparator has a –150-mV threshold. When the body diode conducts, the DTC pin is low. If the body diode does not conduct, the DTC pin is high.

Figure 24. Input-Output Timing Diagram (Turn-On Optimization is Enabled)

To improve noise immunity, the comparator output DTC is blanked when the gate driver output, OUT, is high. The DTC signal always outputs high when OUT is high.

8.3.2 Gate Turnon and Turnoff

Gate turnon is controlled by both the gate driver input, IN, and body-diode conduction. System robustness is enhanced through internal logic that guarantees that OUT is only allowed high if IN is also high. At the IN rising edge, the UCD7138 gate-driver analyzes the DTC signal and determines the required course of action. The OUT pin is sent high immediately if the DTC comparator output is low at the rising edge of the IN signal. If the DTC pin is high at the rising edge of the IN signal, OUT is held low until DTC goes low. To allow the gate turnon edge to optimize freely, setting the dead time between the primary side falling edge and the IN rising edge smaller than expected in the UCD3138A digital controller is recommended.

The gate turnoff edge is determined by the IN signal only. The gate is turned off immediately at the IN falling edge.

8.3.3 V_CC and Undervoltage Lockout

The UCD7138 device has an internal undervoltage-lockout (UVLO) protection feature based on the V_CC-pin voltage. Whenever the driver is in the UVLO condition (such as when the V_CC voltage is less than V_CC(ON) during power up or when the V_CC voltage is less than V_CC(OFF) during power down), the device holds all outputs low, regardless of the status of the inputs. The UVLO voltage is typically 3.8 V with a 240-mV hysteresis. This hysteresis helps prevent chatter when low V_CC supply voltages have noise from the power supply and also when droops occur in the V_CC bias voltage.

For example, at power up, the UCD7138 driver output remains low until the V_CC voltage reaches the UVLO threshold. The magnitude of the OUT signal rises with V_CC until steady-state V_CC is reached. The output remains low until the UVLO threshold is reached. The DTC signal begins to rise when V_CC begins to rise. The internal diode conduction detection comparator remains inactive until V_CC passes V_CC(ON) threshold.

Figure 25. Device Power Up and Power Down

8.3.4 Operating Supply Current

The UCD7138 device features very-low quiescent supply current. The total supply current is the sum of the quiescent supply current, the average I_OUT current from switching, and any current related to pull-up resistors on the unused input pin. Knowing the operating frequency (ƒ_S) and the MOSFET gate (Q_G) charge, the average I_OUT current can be calculated as product of Q_G and ƒ_S.

8.3.5 Driver Stage

The input pins of the UCD7138 device are based on a CMOS-compatible input-threshold logic that is independent of the V_CC supply voltage. The logic-level thresholds can be conveniently driven with PWM control signals derived from 3.3-V.

The output stage of the UCD7138 device features a unique architecture on the pull-up structure. This architecture delivers the highest peak-source current when needed during the Miller-plateau region of the power switch turnon transition (when the power switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-Channel MOSFET and an additional N-Channel MOSFET in parallel. The function of the N-Channel MOSFET is to provide a brief boost in the peak sourcing current to enable fast turnon. This boost occurs by briefly turning on the N-Channel MOSFET when the output is changing state from LOW to HIGH.

Figure 26. Gate-Driver Output Structure

8.4.1 UVLO Mode

When the V_CC voltage to the device has not reached the V_CC(ON) threshold or has fallen below the UVLO threshold, V_CC(OFF) , the device operates in the low-power UVLO mode. In this mode, most internal functions are disabled and the I_CC current is very low. In UVLO mode, the OUT pin is held low. The device passes out of UVLO mode when the V_CC voltage increases above the V_CC(ON) threshold.

8.4.2 Normal Operation Mode

In this mode, the I_CC current is higher because all internal control and timing functions are operating and the gate-driver output, OUT, is driving the controlled MOSFET for synchronous rectification. In this mode, the V_CC current is the sum of I_CC(ON) plus the average current required to drive the load on the OUT pin.