SLUS645F February   2005  – December 2014 UCD7201

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reference / External Bias Supply
      2. 8.3.2 Input Pin
      3. 8.3.3 Current Sensing and Protection
      4. 8.3.4 Handshaking
      5. 8.3.5 Driver Output
      6. 8.3.6 Source/Sink Capabilities During Miller Plateau
      7. 8.3.7 Drive Current and Power Requirements
      8. 8.3.8 Operational Waveforms
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation with VDD < 4.25 V (Minimum VDD)
      2. 8.4.2 Operation with IN Pin Open
      3. 8.4.3 Operation with ILIM Pin Open
      4. 8.4.4 Operation with ILIM Pin High
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Half-Bridge Converter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Intermediate Bus Converter
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

PWP
14 PIN
Top View
PWP_LUS645.gif

Pin Functions

PIN I/O FUNCTION
NO. NAME
1 NC - No Connection
2 3V3 O Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA of current. Place 0.22 μF of ceramic capacitance from this pin to ground.
3 IN1 I The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry from any external noise.
4 AGND - Analog ground return.
5 IN2 I The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry from any external noise.
6 CLF O Current limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the output of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is latched high until the device receives the next rising edge on the IN pin.
7 ILIM I Current limit threshold set pin. The current limit threshold can be set to any value between 0.25 V and 1.0 V. The default value while open is 0.5 V.
8 CS I Current sense pin. Fast current limit comparator connected to the CS pin is used to protect the power stage by implementing cycle-by-cycle current limiting.
9 PGND - Power ground return. The pin should be connected very closely to the source of the power MOSFET.
10 OUT2 O The high-current TrueDrive™ driver output.
11 OUT1 O The high-current TrueDrive™ driver output.
12 PVDD I Supply pin provides power for the output drivers. It is not connected internally to the VDD supply rail. The bypass capacitor for this pin should be returned to PGND.
13 VDD I Supply input pin to power the driver. The UCD7K devices accept an input range of 4.5 V to 15 V. Bypass the pin with at least 4.7 μF of capacitance, returned to AGND.
14 NC - No Connection.