SLVSAN9C April   2011  – March  2019 UCD90120A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C/SMBus/PMBus Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 TI Fusion GUI
      2. 7.3.2 PMBus Interface
      3. 7.3.3 Rail Configuration
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power-Supply Sequencing
        1. 7.4.1.1 Turn-On Sequencing
        2. 7.4.1.2 Turn-Off Sequencing
        3. 7.4.1.3 Sequencing Configuration Options
      2. 7.4.2  Pin-Selected Rail States
      3. 7.4.3  Monitoring
        1. 7.4.3.1 Voltage Monitoring
        2. 7.4.3.2 Current Monitoring
        3. 7.4.3.3 Remote Temperature Monitoring and Internal Temperature Sensor
        4. 7.4.3.4 Temperature by Host Input
      4. 7.4.4  Fault Responses and Alert Processing
      5. 7.4.5  Shut Down All Rails and Sequence On (Resequence)
      6. 7.4.6  GPIOs
      7. 7.4.7  GPO Control
      8. 7.4.8  GPO Dependencies
      9. 7.4.9  GPO Delays
      10. 7.4.10 State Machine Mode Enable
      11. 7.4.11 GPI Special Functions
      12. 7.4.12 Power-Supply Enables
      13. 7.4.13 Cascading Multiple Devices
      14. 7.4.14 PWM Outputs
        1. 7.4.14.1 FPWM1-8
        2. 7.4.14.2 PWM1-4
      15. 7.4.15 Programmable Multiphase PWMs
      16. 7.4.16 Margining
        1. 7.4.16.1 Open-Loop Margining
        2. 7.4.16.2 Closed-Loop Margining
      17. 7.4.17 System Reset Signal
      18. 7.4.18 Watch Dog Timer
      19. 7.4.19 Run Time Clock
      20. 7.4.20 Data and Error Logging to Flash Memory
      21. 7.4.21 Brownout Function
      22. 7.4.22 PMBus Address Selection
    5. 7.5 Programming
      1. 7.5.1 Device Configuration and Programming
        1. 7.5.1.1 Full Configuration Update While in Normal Mode
      2. 7.5.2 JTAG Interface
      3. 7.5.3 Internal Fault Management and Memory Error Correction (ECC)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Estimating ADC Reporting Accuracy
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.22 PMBus Address Selection

Two pins are allocated to decode the PMBus address. At power up, the device applies a bias current to each address-detect pin, and the voltage on that pin is captured by the internal 12-bit ADC. The PMBus address is calculated as follows.

PMBus Address = 12 × bin(VAD01) + bin(VAD00)

Where bin(VAD0x) is the address bin for one of eight addresses as shown in Table 8. The address bins are defined by the MIN and MAX VOLTAGE RANGE (V). Each bin is a constant ratio of 1.25 from the previous bin. This method maintains the width of each bin relative to the tolerance of standard 1% resistors.

Table 8. PMBus Address Bins

ADDRESS BIN RPMBus
PMBus RESISTANCE (kΩ)
open —
11 200
10 154
9 118
8 90.9
7 69.8
6 53.6
5 41.2
4 31.6
short —

A low impedance (short) on either address pin that produces a voltage below the minimum voltage causes the PMBus address to default to address 126 (0x7E). A high impedance (open) on either address pin that produces a voltage above the maximum voltage also causes the PMBus address to default to address 126 (0x7E).

Address 0 is not used because it is the PMBus general-call address. Addresses 11 and 127 can not be used by this device or any other device that shares the PMBus with it, because those are reserved for manufacturing programming and test. It is recommended that address 126 not be used for any devices on the PMBus, because this is the address that the UCD90120A defaults to if the address lines are shorted to ground or left open. Table 9 summarizes which PMBus addresses can be used. Other SMBus/PMBus addresses have been assigned for specific devices. For a system with other types of devices connected to the same PMBus, see the SMBus device address assignments table in Appendix C of the latest version of the System Management Bus (SMBus) specification. The SMBus specification can be downloaded at http://smbus.org/specs/smbus20.pdf.

Table 9. PMBus Address Assignment Rules

ADDRESS STATUS REASON
0 Prohibited SMBus generaladdress call
1-10 Available
11 Avoid Causes conflicts with other devices during program flash updates.
12 Prohibited PMBus alert response protocol
13-125 Available
126 For JTAG Use Default value; may cause conflicts with other devices.
127 Prohibited Used by TI manufacturing for device tests.
UCD90120A det_PMBus_lvsan9.gifFigure 29. PMBus Address-Detection Method

NOTE

Address 126 (0x7E) is not recommended to be selected as a permanent PMBus address for any given application design.

Leaving the address in default state as 126 (0x7E) will enable the JTAG and not allow using the JTAG compatible pins (36-39) as GPIOs.