SLUSDC1 September   2018 UCD90320U

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Application
  4. 4 Revision History
  5. 5 Description Continued
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Non-Volatile Memory Characteristics
    7. 7.7 I2C/PMBus Interface Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 TI Fusion Digital Power Designer software
      2. 8.3.2 PMBUS Interface
      3. 8.3.3 Rail Setup
    4. 8.4 Device Functional Modes
      1. 8.4.1  Rail Monitoring Configuration
      2. 8.4.2  GPI Configuration
      3. 8.4.3  Rail Sequence Configuration
      4. 8.4.4  Fault Responses Configuration
      5. 8.4.5  GPO Configuration
        1. 8.4.5.1 Command Controlled GPO
        2. 8.4.5.2 Logic GPO
      6. 8.4.6  Margining Configuration
      7. 8.4.7  Pin Selected Rail States Configuration
      8. 8.4.8  Watchdog Timer
      9. 8.4.9  System Reset Function
      10. 8.4.10 Cascading Multiple Devices
      11. 8.4.11 Rail Monitoring
      12. 8.4.12 Status Monitoring
      13. 8.4.13 Data and Error Logging to EEPROM Memory
      14. 8.4.14 Black Box First Fault Logging
      15. 8.4.15 PMBus Address Selection
      16. 8.4.16 ADC Reference
      17. 8.4.17 Device Reset
      18. 8.4.18 Brownout
      19. 8.4.19 Internal Fault Management
      20. 8.4.20 Single Event Upset
    5. 8.5 Device Configuration and Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.8 Watchdog Timer

The UCD90320U device provides a watchdog timer (WDT). The WDT can be reset by toggling a watchdog input (WDI) pin. If WDI is not toggled within a programmed period, the WDT times out. As a result, a watchdog output (WDO) pin is asserted (generates a pulse) in order to provide a system-reset signal.

The WDI and WDO pins are GPIO pins and are only optional. The WDI can be replaced by SYSTEM_WATCHDOG_RESET command sent over PMBus. The WDO can be manifested through the Boolean Logic defined GPOs, or its function can be integrated into the system reset pin (RESET) configured in the system reset function. See also the System Reset Function section.

The WDT timer is programmable from 0.001 s to 258.048 s. See also the UCD90320U Sequencer and System Health Controller PMBus Command Reference user guide for details on configuring the watchdog timer.

After a timeout, the WDT can be restarted by toggling the WDI pin or by writing a SYSTEM_WATCHDOG_RESET command over PMBus. Figure 25 shows the watchdog timing waveforms.

UCD90320U watchdog_timer_SLVSCW0.gifFigure 25. Watchdog Timer Operation Timing Diagram

The WDT can be active immediately at power up or after an initial wait time. These are the programmable wait times options that determine when the WDT operation begins.

  • 100 ms
  • 200 ms
  • 400 ms
  • 800 ms
  • 1.6 s
  • 3.2 s
  • 6.4 s
  • 12.8 s
  • 25.6 s
  • 51.2 s
  • 102.4 s
  • 204.8 s
  • 409.6 s
  • 819.2 s
  • 1638.4 s