SLVSC86A January   2014  – March 2014 UCD9244-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Terminal Configuration and Functions
    1.     Terminal Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Handling Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics (Continued)
    7. 7.7  ADC Monitoring Intervals And Response Times
    8. 7.8  Hardware Fault Detection Latency
    9. 7.9  PMBus/SMBus/I2C
    10. 7.10 I2C/SMBus/PMBus Timing Requirements
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  PMBus Interface
      2. 8.3.2  Resistor Programmed PMBus Address Decode
      3. 8.3.3  VID Interface
      4. 8.3.4  Jtag Interface
      5. 8.3.5  Bias Supply Generator (Shunt Regulator Controller)
      6. 8.3.6  Power-On Reset
      7. 8.3.7  External Reset
      8. 8.3.8  ON_OFF_CONFIG
      9. 8.3.9  Output Voltage Adjustment
      10. 8.3.10 Calibration
      11. 8.3.11 Analog Front End (AFE)
      12. 8.3.12 Voltage Sense Filtering
      13. 8.3.13 DPWM Engine
      14. 8.3.14 Rail/Power Stage Configuration
      15. 8.3.15 DPWM Phase Synchronization
      16. 8.3.16 Output Current Measurement
      17. 8.3.17 Current Sense Input Filtering
      18. 8.3.18 Over-Current Detection
      19. 8.3.19 Input Voltage Monitoring
      20. 8.3.20 Input UV Lockout
      21. 8.3.21 Temperature Monitoring
      22. 8.3.22 Auxiliary ADC Input Monitoring
      23. 8.3.23 Soft Start, Soft Stop Ramp Sequence
      24. 8.3.24 Non-Volatile Memory Error Correction Coding
      25. 8.3.25 Data Logging
    4. 8.4 Device Functional Modes
      1. 8.4.1 4-Bit VID Mode
      2. 8.4.2 6-Bit VID Mode
      3. 8.4.3 8-Bit VID Mode
      4. 8.4.4 Current Foldback Mode
  9. 9 Applications and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Automatic System Identification (Auto-ID)
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Digital Compensator
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.10 I2C/SMBus/PMBus Timing Requirements

TJ = –55°C to 125°C, 3V < V33 < 3.6V, typical values at TJ = 25°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
fSMB SMBus/PMBus operating frequency Slave mode; SMBC 50% duty cycle 10 1000 kHz
fI2C I C operating frequency Slave mode; SCL 50% duty cycle 10 1000 kHz
t(BUF) Bus free time between start and stop 5 µs
t(HD:STA) Hold time after (repeated) start 0.3 µs
t(SU:STA) Repeated start setup time 0.3 µs
t(SU:STO) Stop setup time 0.3 µs
t(HD:DAT) Data hold time Receive mode 0 ns
t(SU:DAT) Data setup time 55 ns
t(TIMEOUT) Error signal/detect See (1) 35 ms
t(LOW) Clock low period 0.55 µs
t(HIGH) Clock high period See (2) 0.3 50 µs
t(LOW:SEXT) Cumulative clock low slave extend time See (3) 25 ms
tFALL Clock/data fall time Rise time tRISE = VILMAX – 0.15) to (VIHMIN + 0.15),
TJ = -40°C to 125°C		 1000 ns
tRISE Clock/data rise time Fall time tFALL = 0.9 V33 to (VILMAX – 0.15),
TJ = -40°C to 125°C		 1000 ns
(1) The UCD9244 times out when any clock low exceeds t(TIMEOUT).
(2) t(HIGH) , max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving UCD9244 that is in progress.
(3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.