8.3.23 Soft Start, Soft Stop Ramp Sequence

The UCD9244 performs soft start and soft stop ramps under closed-loop control.

Performing a start or stop ramp or tracking is considered a separate operational mode. The other operational modes are normal regulation and light load regulation. Each operational mode can be configured to have an independent loop gain and compensation. Each set of loop gain coefficients is called a "bank" and is configured using the CLA_GAINS PMBus command.

Start ramps are performed by waiting for the configured start delay TON_DELAY and then ramping the internal reference toward the commanded reference voltage at the rate specified by the TON_RISE time and VOUT_COMMAND. The DPWM outputs are enabled when the internal ramp reference equals the preexisting voltage (pre-bias) on the output and the calculated DPWM pulse width exceeds the pulse width specified by DRIVER_MIN_PULSE. This ensures that a constant ramp rate is maintained, and that the ramp is completed at the same time it would be if there had not been a pre-bias condition.

Figure 12 and Figure 13 show the operation of soft-start and soft-stop ramps.

Figure 12. Soft-Start Ramp

Figure 13. Soft-Stop Ramp

When a voltage rail is in its idle state, the DPWM outputs are disabled, and the differential voltage on the EAP/EAN terminals are monitored by the controller. During idle the Vref DAC is adjusted to match the feedback voltage. If there is a pre-bias (that is, a non-zero voltage on the regulated output), then the device can begin the start ramp from that voltage with a minimum of disturbance. This is done by calculating the duty cycle that is required to match the measured voltage on the rail. Nominally this is calculated as Vout / Vin. If the pre-bias voltage on the output requires a smaller pulse width than the driver can deliver, as defined by the DRIVER_MIN_PULSE PMBus command, then the start ramp is delayed until the internal ramp reference voltage has increased to the point where the required duty cycle exceeds the specified minimum duty.

Once a soft start/stop ramp has begun, the output is controlled by adjusting the Vref DAC at a fixed rate and allowing the digital compensator control engine to generate a duty cycle based on the error. The Vref DAC adjustments are made at a rate of 10 kHz and are based on the TON_RISE or TOFF_FALL PMBus configuration parameters.

Although the presence of a pre-bias voltage or a specified minimum DPWM pulse width affects the time when the DPWM signals become active, the time from when the controller starts processing the turn-on command to the time when it reaches regulation is TON_DELAY plus TON_RISE, regardless of the pre-bias or minimum duty cycle.

During a normal ramp (i.e. no tracking, no current limiting events and no EADC saturation), the set point slews at a pre-calculated rate based on the commanded output voltage and TON_RISE. Under closed loop control, the compensator follows this ramp up to the regulation point.

Because the EADC in the controller has a limited range, it may saturate due to a large transient during a start/stop ramp. If this occurs, the controller overrides the calculated set point ramp value, and adjusts the Vref DAC in the direction to minimize the error. It continues to step the Vref DAC in this direction until the EADC comes out of saturation. Once it is out of saturation, the start ramp continues, but from this new set point voltage; and therefore, has an impact on the ramp time.