SWRS170K March   2014  – November 2023 WL1807MOD , WL1837MOD

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Revision History
  7. 6 Device Comparison
    1. 6.1 Related Products
  8. 7 Terminal Configuration and Functions
    1. 7.1 Pin Attributes
  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  External Digital Slow Clock Requirements
    5. 8.5  Thermal Resistance Characteristics for MOC 100-Pin Package
    6. 8.6  WLAN Performance: 2.4-GHz Receiver Characteristics
    7. 8.7  WLAN Performance: 2.4-GHz Transmitter Power
    8. 8.8  WLAN Performance: 5-GHz Receiver Characteristics
    9. 8.9  WLAN Performance: 5-GHz Transmitter Power
    10. 8.10 WLAN Performance: Currents
    11. 8.11 Bluetooth Performance: BR, EDR Receiver Characteristics—In-Band Signals
    12. 8.12 Bluetooth Performance: Transmitter, BR
    13. 8.13 Bluetooth Performance: Transmitter, EDR
    14. 8.14 Bluetooth Performance: Modulation, BR
    15. 8.15 Bluetooth Performance: Modulation, EDR
    16. 8.16 Bluetooth low energy Performance: Receiver Characteristics – In-Band Signals
    17. 8.17 Bluetooth low energy Performance: Transmitter Characteristics
    18. 8.18 Bluetooth low energy Performance: Modulation Characteristics
    19. 8.19 Bluetooth BR and EDR Dynamic Currents
    20. 8.20 Bluetooth low energy Currents
    21. 8.21 Timing and Switching Characteristics
      1. 8.21.1 Power Management
        1. 8.21.1.1 Block Diagram – Internal DC-DCs
      2. 8.21.2 Power-Up and Shut-Down States
      3. 8.21.3 Chip Top-level Power-Up Sequence
      4. 8.21.4 WLAN Power-Up Sequence
      5. 8.21.5 Bluetooth-Bluetooth low energy Power-Up Sequence
      6. 8.21.6 WLAN SDIO Transport Layer
        1. 8.21.6.1 SDIO Timing Specifications
        2. 8.21.6.2 SDIO Switching Characteristics – High Rate
      7. 8.21.7 HCI UART Shared-Transport Layers for All Functional Blocks (Except WLAN)
        1. 8.21.7.1 UART 4-Wire Interface – H4
      8. 8.21.8 Bluetooth Codec-PCM (Audio) Timing Specifications
  10. 9 Detailed Description
    1. 9.1 WLAN Features
    2. 9.2 Bluetooth Features
    3. 9.3 Bluetooth Low Energy Features
    4. 9.4 Device Certification
      1. 9.4.1 FCC Certification and Statement
      2. 9.4.2 Innovation, Science, and Economic Development Canada (ISED)
      3. 9.4.3 ETSI/CE
      4. 9.4.4 MIC Certification
    5. 9.5 Module Markings
    6. 9.6 Test Grades
    7. 9.7 End Product Labeling
    8. 9.8 Manual Information to the End User
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 Typical Application – WL1837MOD Reference Design
      2. 10.1.2 Design Recommendations
      3. 10.1.3 RF Trace and Antenna Layout Recommendations
      4. 10.1.4 Module Layout Recommendations
      5. 10.1.5 Thermal Board Recommendations
      6. 10.1.6 Baking and SMT Recommendations
        1. 10.1.6.1 Baking Recommendations
        2. 10.1.6.2 SMT Recommendations
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Tools and Software
      3. 11.1.3 Device Support Nomenclature
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 TI Module Mechanical Outline
    2. 12.2 Tape and Reel Information
      1. 12.2.1 Tape and Reel Specification
      2. 12.2.2 Packing Specification
        1. 12.2.2.1 Reel Box
        2. 12.2.2.2 Shipping Box
    3. 12.3 Packaging Information
      1. 12.3.1 PACKAGE OPTION ADDENDUM

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • MOC|100
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1.2 Design Recommendations

This section describes the layout recommendations for the WL1837 module, RF trace, and antenna.

Table 10-2 summarizes the layout recommendations.

Table 10-2 Layout Recommendations Summary
ITEMDESCRIPTION
Thermal
1The proximity of ground vias must be close to the pad.
2Signal traces must not be run underneath the module on the layer where the module is mounted.
3Have a complete ground pour in layer 2 for thermal dissipation.
4Have a solid ground plane and ground vias under the module for stable system and thermal dissipation.
5Increase the ground pour in the first layer and have all of the traces from the first layer on the inner layers, if possible.
6Signal traces can be run on a third layer under the solid ground layer, which is below the module mounting layer.
RF Trace and Antenna Routing
7The RF trace antenna feed must be as short as possible beyond the ground reference. At this point, the trace starts to radiate.
8The RF trace bends must be gradual with an approximate maximum bend of 45° with trace mitered. RF traces must not have sharp corners.
9RF traces must have via stitching on the ground plane beside the RF trace on both sides.
10RF traces must have constant impedance (microstrip transmission line).
11For best results, the RF trace ground layer must be the ground layer immediately below the RF trace. The ground layer must be solid.
12There must be no traces or ground under the antenna section.
13RF traces must be as short as possible. The antenna, RF traces, and modules must be on the edge of the PCB product. The proximity of the antenna to the enclosure and the enclosure material must also be considered.
Supply and Interface
14The power trace for VBAT must be at least 40-mil wide.
15The 1.8-V trace must be at least 18-mil wide.
16Make VBAT traces as wide as possible to ensure reduced inductance and trace resistance.
17If possible, shield VBAT traces with ground above, below, and beside the traces.
18SDIO signals traces (CLK, CMD, D0, D1, D2, and D3) must be routed in parallel to each other and as short as possible (less than 12 cm). In addition, every trace length must be the same as the others. There should be enough space between traces – greater than 1.5 times the trace width or ground – to ensure signal quality, especially for the SDIO_CLK trace. Remember to keep these traces away from the other digital or analog signal traces. TI recommends adding ground shielding around these buses.
19SDIO and digital clock signals are a source of noise. Keep the traces of these signals as short as possible. If possible, maintain a clearance around them.