SBOS375D October   2006  – October 2024 XTR111

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configurations and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Explanation of Pin Functions
      2. 6.3.2 Dynamic Performance
      3. 6.3.3 External Current Limit
      4. 6.3.4 External MOSFET
      5. 6.3.5 Output Error Flag and Disable Input
      6. 6.3.6 Voltage Regulator
      7. 6.3.7 Level Shift of 0V Input and Transconductance Trim
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input Voltage
      2. 7.1.2 Error Flag Delay
      3. 7.1.3 Voltage Output Configuration
      4. 7.1.4 4mA-to-20mA Output
    2. 7.2 Typical Applications
      1. 7.2.1 0mA–20mA Voltage-to-Current Converter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Additional Applications
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Package and Heat Dissipation
        2. 7.4.1.2 Thermal Pad Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DRC|10
  • DGQ|10
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1.2 Thermal Pad Guidelines

The thermal pad must be connected to the same voltage potential as the device GND pin.

Packages with an exposed thermal pad are specifically designed to provide excellent power dissipation, but board layout greatly influences overall heat dissipation. The thermal resistance from junction-to-ambient (TJA) is specified for the packages with the exposed thermal pad soldered to a normalized PCB, as described in the PowerPAD™ Thermally-Enhanced Package application report. See also the EIA/JEDEC Specifications JESD51-0 to 7, the QFN and SON PCB Attachment application report, and the Quad Flatpack No-Lead Logic Packages application report. These documents are available for download at www.ti.com.

Note: All thermal models have an accuracy variation of 20%.

Component population, layout of traces, layers, and air flow strongly influence heat dissipation. Test worst-case load conditions in the real environment to maintain proper thermal conditions. Minimize thermal stress for proper long-term operation with a junction temperature much less than the absolute maximum rating.