ADC324x Dual-Channel, 14-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converters

1 Features

• Dual Channel
• 14-Bit Resolution
• Single Supply: 1.8 V
• Serial LVDS Interface (SLVDS)
• Flexible Input Clock Buffer with Divide-by-1, -2, -4
• SNR = 72.4 dBFS, SFDR = 87 dBc at
  f_IN = 70 MHz
• Ultra-Low Power Consumption:
  • 116 mW/Ch at 125 MSPS
• Channel Isolation: 105 dB
• Internal Dither and Chopper
• Support for Multi-Chip Synchronization
• Pin-to-Pin Compatible with 12-Bit Version
• Package: VQFN-48 (7 mm × 7 mm)

2 Applications

• Multi-Carrier, Multi-Mode Cellular Base Stations
• Radar and Smart Antenna Arrays
• Munitions Guidance
• Motor Control Feedback
• Network and Vector Analyzers
• Communications Test Equipment
• Nondestructive Testing
• Microwave Receivers
• Software-Defined Radios (SDRs)
• Quadrature and Diversity Radio Receivers
• Handheld Radio and Instrumentation

3 Description

The ADC324x are a high-linearity, ultra-low power, dual-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC324x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

1. For all available packages, see the orderable addendum at the end of the datasheet.

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Performance at f_S = 125 MSPS, f_IN = 10 MHz

4 Revision History

Changes from B Revision (March 2015) to C Revision

• Added Digital Inputs section to Digital Characteristics tableGo
• Changed Wake-up time parameter maximum specifications in Timing Requirements: General tableGo
• Updated Figure 19, Figure 20, Figure 23, Figure 24 , Figure 25, and Figure 26Go
• Updated Figure 50 , Figure 51, Figure 54, Figure 55, Figure 56, and Figure 57.Go
• Updated Figure 81, Figure 82, Figure 85, Figure 86, Figure 87, and Figure 88 . Go
• Updated Figure 112, Figure 113, Figure 116, Figure 117, Figure 118, and Figure 119.Go
• Changed Figure 133. Go
• Changed SNR and Clock Jitter section: changed typical thermal noise value and changed Figure 141 to reflect updated thermal noise valueGo
• Changed Table 3Go
• Changed Changed Figure 142Go
• Added Improving Wake-Up Time From Global Power-Down sectionGo
• Changed Table 8: changed FLIP BITS to FLIP WIRE in register 4h, changed bit D7 in row 70A, and added register 13 rowGo
• Changed Summary of Special Mode Registers section: changed title, moved section to correct locationGo
• Changed register 04h descriptionGo
• Changed register 0Ah and 0Bh descriptionsGo
• Added register 13hGo
• Changed register 70Ah to include DIS CLK FILT bit Go

Changes from A Revision (December 2014) to B Revision

• Changed document status from Mixed Status to Production Data: releasing ADC3241 and ADC3242 to Production; changes made to product preview devices Go

Changes from * Revision (July 2014) to A Revision

• Changed document status to Mixed Status Go
• Made changes to product preview data sheet Go

5 Device Comparison Table

6 Pin Configuration and Functions

RGZ Package

48-Pin VQFN

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