The ADC358x is a low noise, ultra-low power 18-bit 65 MSPS high-speed ADC family. Designed for low noise performance, it delivers a noise spectral density of -160 dBFS/Hz combined with excellent linearity and dynamic range. The ADC358x offers very good DC precision together with IF sampling support which makes it suited for a wide range of applications. High-speed control loops benefit from the short latency as low as only 1 clock cycle. The ADC consumes only 119 mW at 65 Msps and its power consumption scales well with lower sampling rates.
The ADC358x uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device supports a one-lane and two-lane option. The ADC358x is a pin to pin compatible family with different speed grades. It comes in a 40-pin QFN package (5 x 5 mm) and supports the extended industrial temperature range from -40 to +105⁰C.
PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
---|---|---|
ADC3583 ADC3582 ADC3581 | WQFN (40) | 5.00 mm x 5.00 mm |
PART NUMBER | RESOLUTION | SAMPLING RATE |
---|---|---|
ADC3583 | 18 BIT | 65 MSPS |
ADC3582 | 18 BIT | 25 MSPS |
ADC3581 | 18 BIT | 10 MSPS |
Changes from Revision * (February 2021) to Revision A (October 2022)
PIN | I/O | Description | |
---|---|---|---|
Name | No. | ||
INPUT/REFERENCE | |||
AINP | 12 | I | Positive analog input, channel A |
AINM | 13 | I | Negative analog input, channel A |
VCM | 8 | O | Common-mode voltage output for the analog inputs, 0.95 V |
VREF | 2 | I | External voltage reference input, 1.6 V |
REFBUF | 4 | I | 1.2 V external voltage reference input for use with internal reference buffer. Internal 100 kΩ pull-up resistor to AVDD. This pin is also used to configure default operating conditions. |
REFGND | 3 | I | Reference ground input, 0 V |
CLOCK | |||
CLKP | 6 | I | Positive differential sampling clock input for the ADC |
CLKM | 7 | I | Negative differential sampling clock input for the ADC |
CONFIGURATION | |||
PDN/SYNC | 1 | I | Power down/Synchronization input. This pin can be configured via the SPI interface. Active high. This pin has an internal 21 kΩ pull-down resistor. |
RESET | 9 | I | Hardware reset. Active high. This pin has an internal 21 kΩ pull-down resistor. |
SEN | 16 | I | Serial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD. |
SCLK | 35 | I | Serial interface clock input. This pin has an internal 21 kΩ pull-down resistor. |
SDIO | 10 | I/O | Serial interface data input and output. This pin has an internal 21 kΩ pull-down resistor. |
NC | 27,38,39 | - | Do not connect |
DIGITAL INTERFACE | |||
DA0P | 20 | O | Positive differential serial LVDS output for lane 0, channel A. |
DA0M | 19 | O | Negative differential serial LVDS output for lane 0, channel A. |
DA1P | 18 | O | Positive differential serial LVDS output for lane 1, channel A. |
DA1M | 17 | O | Negative differential serial LVDS output for lane 1, channel A. |
DB0P | 31 | O | Positive differential serial LVDS output for lane 0, channel B. Used only in dual band complex decimation. Default is powered down. |
DB0M | 32 | O | Negative differential serial LVDS output for lane 0, channel B. Used only in dual band complex decimation. Default is powered down. |
DB1P | 33 | O | Positive differential serial LVDS output for lane 1, channel B. Used only in dual band complex decimation. Default is powered down. |
DB1M | 34 | O | Negative differential serial LVDS output for lane 1, channel B. Used only in dual band complex decimation. Default is powered down. |
DCLKP | 23 | O | Positive differential serial LVDS bit clock output. |
DCLKM | 22 | O | Negative differential serial LVDS bit clock output. |
FCLKP | 28 | O | Positive differential serial LVDS frame clock output. |
FCLKM | 29 | O | Negative differential serial LVDS frame clock output. |
DCLKINP | 25 | I | Positive differential serial LVDS bit clock input. Internal 100 Ω differential termination. |
DCLKINM | 24 | I | Negative differential serial LVDS bit clock input. Internal 100 Ω differential termination. |
POWER SUPPLY | |||
AVDD | 5,15,36 | I | Analog 1.8 V power supply |
GND | 11,14,37,40, PowerPad | I | Ground, 0 V |
IOVDD | 21,30 | I | 1.8 V power supply for digital interface |
IOGND | 26 | I | Ground, 0 V for digital interface |