The ADCS7476, ADCS7477, and ADCS7478 devices are low power, monolithic CMOS 12-, 10-, and 8-bit analog-to-digital converters that operate at 1 MSPS. The ADCS747x devices are a drop-in replacement for Analog Device's AD747x. Each device is based on a successive approximation register architecture with internal track-and-hold. The serial interface is compatible with several standards, such as SPI, QSPI, MICROWIRE, and many common DSP serial interfaces.
The ADCS747x uses the supply voltage as a reference, enabling the device to operate with a full-scale input range of 0 to VDD. The conversion rate is determined from the serial clock (SCLK) speed. These converters offer a shutdown mode, which can be used to trade throughput for power consumption. The ADCS747x is operated with a single supply that can range from 2.7 V to 5.25 V. Normal power consumption during continuous conversion, using a 3-V or 5-V supply, is 2 mW or 10 mW respectively. The power-down feature, which is enabled by a chip select (CS) pin, reduces the power consumption to under 5 µW using a 5-V supply. All three converters are available in a 6-pin SOT-23 package, which provides an extremely small footprint for applications where space is a critical consideration. These products are designed for operation over the automotive and extended industrial temperature range of −40°C to 125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADCS7476 ADCS7477 ADCS7478 |
SOT-23 (6) | 1.60 mm × 2.90 mm |
Changes from F Revision (March 2013) to G Revision
Changes from E Revision (March 2013) to F Revision
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VDD | P | Positive supply pin. These pins must be connected to a quiet 2.7-V to 5.25-V source and bypassed to GND with 0.1-µF and 1-µF monolithic capacitors placed within 1 cm of the power pin. ADCS747x uses this power supply as a reference, so it must be thoroughly bypassed. |
2 | GND | G | The ground return for the supply. |
3 | VIN | I | Analog input. This signal can range from 0 V to VDD. |
4 | SCLK | I | Digital clock input. The range of frequencies for this input is 10 kHz to 20 MHz, with ensured performance at 20 MHz. This clock directly controls the conversion and readout processes. |
5 | SDATA | O | Digital data output. The output words are clocked out of this pin by the SCLK pin. |
6 | CS | I | Chip select. A conversion process begins on the falling edge of CS. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage, VDD | –0.3 | 6.5 | V | |
Voltage on any analog pin to GND | –0.3 | VDD + 0.3 | V | |
Voltage on any digital pin to GND | –0.3 | 6.5 | V | |
Input current at any pin (except power supply pins) | ±10 | mA | ||
Soldering temperature, infrared (10 sec) | 215 | °C | ||
Operating temperature, TA | 150 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±3500 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±200 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD | Supply voltage | 2.7 | 5.25 | V |
Digital input pins voltage (independent of supply voltage) | 2.7 | 5.25 | V | |
TA | Operating temperature | –40 | 125 | °C |
THERMAL METRIC(1) | ADCS7476, ADCS7477, ADCS7478 | UNIT | |
---|---|---|---|
DBV (SOT-23) | |||
6 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 184.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 151.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 29.7 | °C/W |
ψJT | Junction-to-top characterization parameter | 29.8 | °C/W |
ψJB | Junction-to-board characterization parameter | 29.1 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
STATIC CONVERTER CHARACTERISTICS | |||||||
Resolution with no missing codes | –40°C ≤ TA ≤ 85°C | 10 | Bits | ||||
INL | Integral non-linearity | TA = 25°C | ±0.2 | LSB | |||
–40°C ≤ TA ≤ 85°C | ±0.7 | ||||||
DNL | Differential non-linearity | TA = 25°C | –0.2 | 0.3 | LSB | ||
T–40°C ≤ TA ≤ 85°C | ±0.7 | ±0.7 | |||||
VOFF | Offset error | TA = 25°C | ±0.1 | LSB | |||
–40°C ≤ TA ≤ 85°C | ±0.7 | ||||||
GE | Gain error | TA = 25°C | ±0.2 | LSB | |||
–40°C ≤ TA ≤ 85°C | ±1 | ||||||
DYNAMIC CONVERTER CHARACTERISTICS | |||||||
SINAD | Signal-to-noise plus distortion ratio | fIN = 100 kHz | TA = 25°C | 61.7 | dBFS | ||
–40°C ≤ TA ≤ 85°C | 61 | ||||||
SNR | Signal-to-noise ratio | fIN = 100 kHz | 62 | dB | |||
THD | Total harmonic distortion | fIN = 100 kHz | TA = 25°C | –77 | dB | ||
–40°C ≤ TA ≤ 85°C | –73 | ||||||
SFDR | Spurious-free dynamic range | fIN = 100 kHz | TA = 25°C | 78 | dB | ||
–40°C ≤ TA ≤ 85°C | 74 | ||||||
IMD | Intermodulation distortion, second order terms |
fa = 103.5 kHz, fb = 113.5 kHz | –78 | dB | |||
Intermodulation distortion, third order terms |
fa = 103.5 kHz, fb = 113.5 kHz | –78 | dB | ||||
FPBW | –3-dB full power bandwidth | 5-V supply | 11 | MHz | |||
3-V supply | 8 | MHz | |||||
POWER SUPPLY CHARACTERISTICS | |||||||
IDD | Normal mode (static) | VDD = 4.75 V to 5.25 V, SCLK On or Off | 2 | mA | |||
VDD = 2.7 V to 3.6 V, SCLK On or Off | 1 | mA | |||||
Normal mode (operational) | VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS |
TA = 25°C | 2 | mA | |||
–40°C ≤ TA ≤ 85°C | 3.5 | ||||||
VDD = 2.7 V to 3.6 V, fSAMPLE = 1 MSPS |
TA = 25°C | 0.6 | mA | ||||
–40°C ≤ TA ≤ 85°C | 1.6 | ||||||
Shutdown mode | VDD = 5 V, SCLK Off | 0.5 | µA | ||||
VDD = 5 V, SCLK On | 60 | ||||||
PD | Power consumption, normal mode (operational) |
VDD = 5 V, fSAMPLE = 1 MSPS |
TA = 25°C | 10 | mW | ||
–40°C ≤ TA ≤ 85°C | 17.5 | ||||||
VDD = 3 V, fSAMPLE = 1 MSPS |
TA = 25°C | 2 | mW | ||||
–40°C ≤ TA ≤ 85°C | 4.8 | ||||||
Power consumption, shutdown mode |
VDD = 5 V, SCLK Off | 2.5 | µW | ||||
VDD = 3 V, SCLK Off | 1.5 | ||||||
ANALOG INPUT CHARACTERISTICS | |||||||
VIN | Input range | 0 to VDD | V | ||||
IDCL | DC leakage current | TA = −40°C to 85°C | ±1 | µA | |||
CINA | Analog input capacitance | 30 | pF | ||||
DIGITAL INPUT CHARACTERISTICS | |||||||
VIH | Input high voltage | TA = −40°C to 85°C | 2.4 | V | |||
VIL | Input low voltage | VDD = 5 V, –40°C ≤ TA ≤ 85°C | 0.8 | V | |||
VDD = 3 V, –40°C ≤ TA ≤ 85°C | 0.4 | V | |||||
IIN | Input current | VIN = 0 V or VDD | TA = 25°C | ±10 | nA | ||
–40°C ≤ TA ≤ 85°C | ±1 | µA | |||||
CIND | Digital input capacitance | TA = 25°C | 2 | pF | |||
–40°C ≤ TA ≤ 85°C | 4 | ||||||
DIGITAL OUTPUT CHARACTERISTICS | |||||||
VOH | Output high voltage | ISOURCE = 200 µA, VDD = 2.7 V to 5.25 V, –40°C ≤ TA ≤ 85°C |
VDD – 0.2 | V | |||
VOL | Output low voltage | ISINK = 200 µA, –40°C ≤ TA ≤ 85°C | 0.4 | V | |||
IOL | TRI-STATE leakage current | –40°C ≤ TA ≤ 85°C | ±10 | µA | |||
COUT | TRI-STATE output capacitance | TA = 25°C | 2 | pF | |||
–40°C ≤ TA ≤ 85°C | 4 | ||||||
Output coding | Straight (natural) binary | ||||||
AC ELECTRICAL CHARACTERISTICS | |||||||
fSCLK | Clock frequency | –40°C ≤ TA ≤ 85°C | 20 | MHz | |||
DC | SCLK duty cycle | –40°C ≤ TA ≤ 85°C | 40% | 60% | |||
tTH | Track or hold acquisition time | –40°C ≤ TA ≤ 85°C | 400 | ns | |||
fRATE | Throughput rate | –40°C ≤ TA ≤ 85°C | 1 | MSPS | |||
tAD | Aperture delay | 3 | ns | ||||
tAJ | Aperture jitter | 30 | ps |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
STATIC CONVERTER CHARACTERISTICS | |||||||
Resolution with no missing codes | –40°C ≤ TA ≤ 85°C | 8 | Bits | ||||
INL | Integral non-linearity | TA = 25°C | ±0.05 | LSB | |||
–40°C ≤ TA ≤ 85°C | ±0.3 | ||||||
DNL | Differential non-linearity | TA = 25°C | ±0.07 | LSB | |||
–40°C ≤ TA ≤ 85°C | ±0.3 | ||||||
VOFF | Offset error | TA = 25°C | ±0.03 | LSB | |||
–40°C ≤ TA ≤ 85°C | ±0.3 | ||||||
GE | Gain error | TA = 25°C | ±0.08 | LSB | |||
–40°C ≤ TA ≤ 85°C | ±0.4 | ||||||
Total unadjusted error | TA = 25°C | ±0.07 | LSB | ||||
–40°C ≤ TA ≤ 85°C | ±0.3 | ||||||
DYNAMIC CONVERTER CHARACTERISTICS | |||||||
SINAD | Signal-to-noise plus distortion ratio | fIN = 100 kHz | TA = 25°C | 49.7 | dB | ||
–40°C ≤ TA ≤ 85°C | 49 | ||||||
SNR | Signal-to-noise ratio | fIN = 100 kHz | 49.7 | dB | |||
THD | Total harmonic distortion | fIN = 100 kHz | TA = 25°C | –77 | dB | ||
–40°C ≤ TA ≤ 85°C | –65 | ||||||
SFDR | Spurious-free dynamic range | fIN = 100 kHz | TA = 25°C | 69 | dB | ||
–40°C ≤ TA ≤ 85°C | 65 | ||||||
IMD | Intermodulation distortion, second order terms |
fa = 103.5 kHz, fb = 113.5 kHz | –68 | dB | |||
Intermodulation distortion, third order terms |
fa = 103.5 kHz, fb = 113.5 kHz | –68 | dB | ||||
FPBW | –3-dB full power bandwidth | 5-V supply | 11 | MHz | |||
3-V supply | 8 | MHz | |||||
POWER SUPPLY CHARACTERISTICS | |||||||
IDD | Normal mode (static) | VDD = 4.75 V to 5.25 V, SCLK On or Off | 2 | mA | |||
VDD = 2.7 V to 3.6 V, SCLK On or Off | 1 | mA | |||||
Normal mode (operational) | VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS |
TA = 25°C | 2 | mA | |||
–40°C ≤ TA ≤ 85°C | 3.5 | ||||||
VDD = 2.7 V to 3.6 V, fSAMPLE = 1 MSPS |
TA = 25°C | 0.6 | mA | ||||
–40°C ≤ TA ≤ 85°C | 1.6 | ||||||
Shutdown mode | VDD = 5 V, SCLK Off | 0.5 | µA | ||||
VDD = 5 V, SCLK On | 60 | ||||||
PD | Power consumption, normal mode (operational) |
VDD = 5 V, fSAMPLE = 1 MSPS |
TA = 25°C | 10 | mW | ||
–40°C ≤ TA ≤ 85°C | 17.5 | ||||||
VDD = 3 V, fSAMPLE = 1 MSPS |
TA = 25°C | 2 | mW | ||||
–40°C ≤ TA ≤ 85°C | 4.8 | ||||||
Power consumption, shutdown mode |
VDD = 5 V, SCLK Off | 2.5 | µW | ||||
VDD = 3 V, SCLK Off | 1.5 | ||||||
ANALOG INPUT CHARACTERISTICS | |||||||
VIN | Input range | 0 to VDD | V | ||||
IDCL | DC leakage current | –40°C ≤ TA ≤ 85°C | ±1 | µA | |||
CINA | Analog input capacitance | 30 | pF | ||||
DIGITAL INPUT CHARACTERISTICS | |||||||
VIH | Input high voltage | –40°C ≤ TA ≤ 85°C | 2.4 | V | |||
VIL | Input low voltage | VDD = 5 V, –40°C ≤ TA ≤ 85°C | 0.8 | V | |||
VDD = 3 V, –40°C ≤ TA ≤ 85°C | 0.4 | V | |||||
IIN | Digital input current | VIN = 0 V or VDD | TA = 25°C | ±10 | nA | ||
–40°C ≤ TA ≤ 85°C | ±1 | µA | |||||
CIND | Input capacitance | TA = 25°C | 2 | p | |||
–40°C ≤ TA ≤ 85°C | 4 | ||||||
DIGITAL OUTPUT CHARACTERISTICS | |||||||
VOH | Output high voltage | ISOURCE = 200 µA, VDD = 2.7 V to 5.25 V, –40°C ≤ TA ≤ 85°C |
VDD − 0.2 | V | |||
VOL | Output low voltage | ISINK = 200 µA, –40°C ≤ TA ≤ 85°C | 0.4 | V | |||
IOL | TRI-STATE leakage current | –40°C ≤ TA ≤ 85°C | ±10 | µA | |||
COUT | TRI-STATE output capacitance | 2 | 4 | pF | |||
Output coding | Straight (natural) binary | ||||||
AC ELECTRICAL CHARACTERISTICS | |||||||
fSCLK | Clock frequency | –40°C ≤ TA ≤ 85°C | 20 | MHz | |||
DC | SCLK duty cycle | –40°C ≤ TA ≤ 85°C | 40% | 60% | |||
tTH | Track or hold acquisition time | –40°C ≤ TA ≤ 85°C | 400 | ns | |||
fRATE | Throughput rate | –40°C ≤ TA ≤ 85°C (see Application Information) | 1 | MSPS | |||
tAD | Aperture delay | 3 | ns | ||||
tAJ | Aperture jitter | 30 | ps |
PARAMETER | CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tCONVERT | TA = 25°C | 16 × tSCLK | ||||
tQUIET | Quiet time(2) | 50 | ns | |||
t1 | Minimum CS pulse width | 10 | ns | |||
t2 | CS to SCLK setup time | 10 | ns | |||
t3 | Delay from CS until SDATA TRI-STATE disabled (3) | 20 | ns | |||
t4 | Data access time after SCLK falling edge(4) | VDD = 2.7 V to 3.6 V | 40 | ns | ||
VDD = 4.75 V to 5.25 V | 20 | ns | ||||
t5 | SCLK low pulse width | 0.4 × tSCLK | ns | |||
t6 | SCLK high pulse width | 0.4 × tSCLK | ns | |||
t7 | SCLK to data valid hold time | VDD = 2.7 V to 3.6 V | 7 | ns | ||
VDD = 4.75 V to 5.25 V | 5 | ns | ||||
t8 | SCLK falling edge to SDATA high impedance (5) | VDD = 2.7 V to 3.6 V | 6 | 25 | ns | |
VDD = 4.75 V to 5.25 V | 5 | 25 | ns | |||
tPOWER-UP | Power-up time from full power down | TA = 25°C | 1 | µs |
The ADCS747x devices are successive-approximation analog-to-digital converters designed around a charge-redistribution digital-to-analog converter. Simplified schematics of the ADCS747x in both track and hold operation are shown in Figure 25 and Figure 26. In Figure 26, the device is in track mode where the switch SW1 connects the sampling capacitor to the input, and SW2 balances the comparator inputs. The device is in this state until CS is brought low, at which point the device moves to hold mode.
Serial interface timing diagrams for the ADCS747x are shown in Figure 2, Figure 3, and Figure 4. CS is chip select, which initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. SDATA is the serial data out pin, where a conversion result is found.
Basic operation of the ADCS747x begins with CS going low, which initiates a conversion process and data transfer. Subsequent rising and falling edges of SCLK will be labeled with reference to the falling edge of CS; for example, the third falling edge of SCLK shall refer to the third falling edge of SCLK after CS goes low.
At the fall of CS, the SDATA pin comes out of TRI-STATE, and the converter moves from track mode to hold mode. The input signal is sampled and held for conversion at the falling edge of CS. The converter moves from hold mode to track mode on the 13th rising edge of SCLK (see Figure 2, Figure 3, or Figure 4). The SDATA pin is placed back into TRI-STATE after the 16th falling edge of SCLK, or at the rising edge of CS, whichever occurs first. After a conversion is completed, the quiet time tQUIET must be satisfied before bringing CS low again to begin another conversion.
Sixteen SCLK cycles are required to read a complete sample from the ADCS747x. The sample bits (including any leading or trailing zeroes) are clocked out on falling edges of SCLK, and are intended to be clocked in by a receiver on subsequent falling edges of SCLK. ADCS747x produces four leading zeroes on SDATA, followed by twelve, ten, or eight data bits (the most significant first). After the data bits, the ADCS7477 clocks out two trailing zeros, and the ADCS7478 clocks out four trailing zeros. The ADCS7476 does not clock out any trailing zeros; the least significant data bit is valid on the 16th falling edge of SCLK.
Depending upon the application, the first edge on SCLK after CS goes low may be either a falling edge or a rising edge. If the first SCLK edge after CS goes low is a rising edge, all four leading zeroes are valid on the first four falling edges of SCLK. If instead the first SCLK edge after CS goes low is a falling edge, the first leading zero may not be set up in time for a microprocessor or DSP to read it correctly. The remaining data bits are still clocked out on the falling edges of SCLK.
Figure 25 shows the device in hold mode where the switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The device moves from hold mode to track mode (Figure 26) on the 13th rising edge of SCLK.
The output format of ADCS747x is straight binary. Code transitions occur midway between successive integer LSB values. The LSB widths for the ADCS7476 is VDD / 4096; for the ADCS7477 the LSB width is VDD / 1024; for the ADCS7478, the LSB width is VDD / 256. The ideal transfer characteristic for the ADCS7476 and ADCS7477 is shown in Figure 27, while the ideal transfer characteristic for the ADCS7478 is shown in Figure 28.
The ADCS747x typically requires 1 µs to power up, either after first applying VDD, or after returning to normal mode from shutdown mode. This corresponds to one dummy conversion for any SCLK frequency within the specifications in this document. After this first dummy conversion, the ADCS747x performs conversions properly.
NOTE
The tQUIET time must still be included between the first dummy conversion and the second valid conversion.
The ADCS747x has two possible modes of operation: Normal Mode and Shutdown Mode. ADCS747x enters normal mode (and a conversion process is begun) when CS is pulled low. The device enters shutdown mode if CS is pulled high before the tenth falling edge of SCLK after CS is pulled low, or stays in normal mode if CS remains low. Once in shutdown mode, the device stays there until CS is brought low again. By varying the ratio of time spent in the normal and shutdown modes, a system may trade off throughput for power consumption.
The best possible throughput is obtained by leaving the ADCS747x in normal mode at all times, so there are no power-up delays. To keep the device in normal mode continuously, CS must be kept low until after the 10th falling edge of SCLK after the start of a conversion (remember that a conversion is initiated by bringing CS low).
If CS is brought high after the 10th falling edge, but before the 16th falling edge, the device remains in normal mode, but the current conversion is aborted, and SDATA returns to TRI-STATE (truncating the output word).
Sixteen SCLK cycles are required to read all of a conversion word from the device. After sixteen SCLK cycles have elapsed, CS may be idled either high or low until the next conversion. If CS is idled low, it must be brought high again before the start of the next conversion, which begins when CS is again brought low.
After sixteen SCLK cycles, SDATA returns to TRI-STATE. Another conversion may be started, after tQUIET has elapsed, by bringing CS low again.
When the VDD supply is first applied, the ADCS747x may power up in either of the two modes: normal or shutdown. As such, one dummy conversion should be performed after start-up, exactly as described in Power-Up Timing. The part may then be placed into either normal mode or the shutdown mode, as described in Normal Mode and Shutdown Mode.
Shutdown mode is appropriate for applications that either do not sample continuously, or are willing to trade throughput for power consumption. When the ADCS747x is in shutdown mode, all of the analog circuitry is turned off.
To enter shutdown mode, a conversion must be interrupted by bringing CS back high anytime between the second and tenth falling edges of SCLK, as shown in Figure 29. Once CS has been brought high in this manner, the device enters shutdown mode; the current conversion is aborted and SDATA enters TRI-STATE. If CS is brought high before the second falling edge of SCLK, the device does not change mode; this is to avoid accidentally changing mode as a result of noise on the CS line.
To exit shutdown mode, bring CS back low. Upon bringing CS low, the ADCS747x begins powering up. Power up typically takes 1 µs. This microsecond of power-up delay results in the first conversion result being unusable. The second conversion performed after power-up, however, is valid, as shown in Figure 30.
If CS is brought back high before the 10th falling edge of SCLK, the device returns to shutdown mode. This is done to avoid accidentally entering normal mode as a result of noise on the CS line. To exit shutdown mode and remain in normal mode, CS must be kept low until after the 10th falling edge of SCLK. The ADCS747x is fully powered up after 16 SCLK cycles.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
A typical application of ADCS747x is shown in Figure 32. The combined analog and digital supplies are provided in this example by the TI LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages. The supply is bypassed with a capacitor network located close to the device. The three-wire interface is also shown connected to a microprocessor or DSP.
An equivalent circuit for the ADCS747x input channel is shown in Figure 31. The diodes D1 and D2 provide ESD protection for the analog inputs. At no time should an analog input exceed VDD + 300 mV or GND – 300 mV, as these ESD diodes begin conducting current into the substrate or supply line and affect ADC operation.
The capacitor C1 in Figure 31 typically has a value of 4 pF, and is mainly due to pin capacitance. The resistor R1 represents the ON resistance of the multiplexer and track or hold switch, and is typically 100 Ω. The capacitor C2 is the ADCS747x sampling capacitor, and is typically 26 pF.
The sampling nature of the analog input causes input current pulses that result in voltage spikes at the input. ADCS747x delivers best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance. In some applications where dynamic performance is critical, the input must be driven with a low output-impedance amplifier. In addition, when using ADCS747x to sample AC signals, a band-pass or low-pass filter reduces harmonics and noise and thus improve THD and SNR.
The ADCS747x digital inputs (SCLK and CS) are not limited by the same absolute maximum ratings as the analog inputs. The digital input pins are instead limited to 6.5 V with respect to GND, regardless of VDD, the supply voltage. This allows ADCS747x to be interfaced with a wide range of logic levels, independent of the supply voltage.
NOTE
Even though the digital inputs are tolerant of up to 6.5 V above GND, the digital outputs are only capable of driving VDD out.
In addition, the digital input pins are not prone to latch-up; SCLK and CS may be asserted before VDD without any risk.
The ADCS747x are monolithic CMOS 12-, 10-, and 8-bit ADCs that use the supply voltage as a reference, enabling the devices to operate with a full-scale input range of 0 to VDD. An example low-power application with the LMT87, which is a wide range ±0.3°C accurate temperature sensor, is shown in Figure 32.
A successful ADCS747x and LMT87 design is constrained by the following factors:
Designing for an accurate measurement requires careful attention to the timing requirements for the ADCS747x parts.
Because the ADC747x parts use the supply voltage as a reference, ensuring that the supply voltage is settled to its final level before exiting the shutdown mode and beginning a conversion is important. After the supply voltage has settled, the CS is brought to a low level (ideally 0 V) to start a conversion.
Ensuring that any noise on the power supply is less than ½ LSB in amplitude is also important. The supply voltage must be regarded as a precise voltage reference.
After the CS has been brought low, the user must wait for one complete conversion cycle (approximately 1 μs) for meaningful data. The dummy conversion cycle is the start-up time of the ADCS747x. The ADCS747x digital output can then be correlated to the LMT87 output level to get an accurate temperature reading. At VDD = 3.3 V,
1 LSB of ADCS7476 is 0.805 mV.