SBAS607B April   2016  – September 2016 ADS127L01

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Serial Interface
    7. 6.7  Switching Characteristics: Serial Interface Mode
    8. 6.8  Timing Requirements: Frame-Sync Master Mode
    9. 6.9  Switching Characteristics: Frame-Sync Master Mode
    10. 6.10 Timing Requirements: Frame-Sync Slave Mode
    11. 6.11 Switching Characteristics: Frame-Sync Slave Mode
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs (AINP, AINN)
      2. 8.3.2 Digital Filter
        1. 8.3.2.1 Low-Latency Filter
          1. 8.3.2.1.1 Low-Latency Filter Frequency Response
          2. 8.3.2.1.2 Low-Latency Filter Settling Time
        2. 8.3.2.2 Wideband Filter
          1. 8.3.2.2.1 Wideband Filters Frequency Response
          2. 8.3.2.2.2 Wideband Filters Settling Time
      3. 8.3.3 Voltage Reference Inputs (REFP, REFN)
      4. 8.3.4 Clock Input (CLK)
      5. 8.3.5 Out-of-Range-Detect System Monitor
      6. 8.3.6 System Calibration
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes (HR, LP, VLP)
      2. 8.4.2 Hardware Mode Pins
        1. 8.4.2.1 Interface Selection Pins (FORMAT, FSMODE)
        2. 8.4.2.2 Digital-Filter Path Selection Pins (FILTER[1:0])
        3. 8.4.2.3 Oversampling Ratio Selection Pins (OSR[1:0])
      3. 8.4.3 Start Pin (START)
      4. 8.4.4 Reset and Power-Down Pin (RESET/PWDN)
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI) Programming
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Ready (DRDY/FSYNC)
        4. 8.5.1.4 Data Input (DIN)
        5. 8.5.1.5 Data Output (DOUT)
        6. 8.5.1.6 Daisy-Chain Input (DAISYIN)
        7. 8.5.1.7 SPI Timeout
        8. 8.5.1.8 SPI Commands
          1. 8.5.1.8.1 RESET (0000 011x)
          2. 8.5.1.8.2 START (0000 100x)
          3. 8.5.1.8.3 STOP (0000 101x)
          4. 8.5.1.8.4 RDATA (0001 0010)
          5. 8.5.1.8.5 RREG (0010 rrrr 0000 nnnn)
          6. 8.5.1.8.6 WREG (0100 rrrr 0000 nnnn)
      2. 8.5.2 Frame-Sync Programming
        1. 8.5.2.1 Frame-Sync Master Mode
          1. 8.5.2.1.1 Chip Select (CS) in Frame-Sync Master Mode
          2. 8.5.2.1.2 Serial Clock (SCLK) in Frame-Sync Master Mode
          3. 8.5.2.1.3 Frame-Sync (DRDY/FSYNC) in Frame-Sync Master Mode
          4. 8.5.2.1.4 Data Input (DIN) in Frame-Sync Master Mode
          5. 8.5.2.1.5 Data Output (DOUT) in Frame-Sync Master Mode
          6. 8.5.2.1.6 Daisy-Chain Input (DAISYIN) in Frame-Sync Master Mode
        2. 8.5.2.2 Frame-Sync Slave Mode
          1. 8.5.2.2.1 Chip Select (CS) in Frame-Sync Slave Mode
          2. 8.5.2.2.2 Serial Clock (SCLK) in Frame-Sync Slave Mode
          3. 8.5.2.2.3 Frame-Sync (DRDY/FSYNC) in Frame-Sync Slave Mode
          4. 8.5.2.2.4 Data Input (DIN) in Frame-Sync Slave Mode
          5. 8.5.2.2.5 Data Output (DOUT) in Frame-Sync Slave Mode
          6. 8.5.2.2.6 Daisy-Chain Input (DAISYIN) in Frame-Sync Slave Mode
      3. 8.5.3 Data Format
      4. 8.5.4 Status Word
      5. 8.5.5 Cyclic Redundancy Check (CRC)
        1. 8.5.5.1 Computing the CRC
    6. 8.6 Register Maps
      1. 8.6.1 ID: ID Control Register (address = 00h) [reset = x3h]
      2. 8.6.2 CONFIG: ADC Configuration Register (address = 01h) [reset = 00h]
      3. 8.6.3 OFC0: System Offset Calibration Register 0 (address = 02h) [reset = 00h]
      4. 8.6.4 OFC1: System Offset Calibration Register 1 (address = 03h) [reset = 00h]
      5. 8.6.5 OFC2: System Offset Calibration Register 2 (address = 04h) [reset = 00h]
      6. 8.6.6 FSC0: System Gain Calibration Register 0 (address = 05h) [reset = 00h]
      7. 8.6.7 FSC1: System Gain Calibration Register 1 (address = 06h) [reset = 80h]
      8. 8.6.8 MODE: Mode Settings (address = 07h) [reset = xxh]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Multiple Device Configuration
        1. 9.1.2.1 Cascaded Configuration
          1. 9.1.2.1.1 SPI interface Mode
          2. 9.1.2.1.2 Frame-Sync interface Mode
        2. 9.1.2.2 Daisy-Chain Configuration
          1. 9.1.2.2.1 Daisy-Chain Operation Using SPI interface Mode
          2. 9.1.2.2.2 Daisy-Chain Operation Using Frame-Sync interface Mode
        3. 9.1.2.3 Synchronizing Devices
      3. 9.1.3 ADC Input Driver
        1. 9.1.3.1 Antialiasing Filter
        2. 9.1.3.2 Input Driver Selection
        3. 9.1.3.3 Amplifier Stability
      4. 9.1.4 Modulator Saturation
      5. 9.1.5 ADC Reference Driver
        1. 9.1.5.1 Single Chip Solution: REF6xxx
        2. 9.1.5.2 Multichip Solution: REF50xx + OPA320
      6. 9.1.6 Driving LVDD With an External Supply
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Initialization Setup
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Sequencing
    2. 10.2 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Data Rates: Up to 512 kSPS
  • AC + DC Performance:
    • Passband: Up to 230 kHz
    • SNR: Up to 115.5 dB
    • THD: Down to -129 dB
    • DC Accuracy:
    • Offset Drift: 1.5 μV/°C
    • Gain Drift: 0.2 ppm/°C
  • Operating Modes:
    • High-resolution (128 kSPS at 26 mW)
    • Low-power (128 kSPS at 15 mW)
    • Very-low Power: 105 dB SNR (128 kSPS at 9 mW)
  • Digital Filter Options:
    • Low-latency Filter: Sinc Frequency Response
    • Wideband 1 Filter:
      (0.45 to 0.55) × fDATA Transition Band
    • Wideband 2 Filter:
      (0.40 to 0.50) × fDATA Transition Band
  • SPI™ or Frame-Sync Serial Interface
    • Daisy-Chain Compatible
  • Analog Supply: 2.7 V to 3.6 V
  • Digital Supply: 1.7 V to 3.6 V
  • Operating Temperature: –40°C to +125°C

2 Applications

  • Vibration and Modal Analysis
  • Data Acquisition Systems
  • Acoustics and Dynamic Strain Gauges
  • Power Quality Analysis

3 Description

The ADS127L01 is a 24-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) with data rates up to 512 kSPS. This device offers a unique combination of excellent dc accuracy and outstanding ac performance. The high-order, chopper-stabilized modulator achieves very low drift with low in-band noise. The integrated decimation filter suppresses modulator out-of-band noise. In addition to al low-latency filter, the ADS127L01 provides multiple Wideband filters with less than ±0.00004 dB of ripple, and an option for –116-dB stop-band attenuation at the Nyquist rate.

Traditionally, industrial delta-sigma ADCs that offer good drift performance use digital filters with large passband droop. As a result, industrial delta-sigma ADCs have limited signal bandwidth and are mostly suited for dc measurements. High-resolution ADCs in audio applications offer larger usable bandwidths, but the offset and drift specifications are significantly weaker than industrial counterparts. The ADS127L01 combines these converters, providing high-precision industrial measurement with excellent dc and ac specifications over an extended industrial temperature range of –40°C to +125°C.

A variety of operating modes allow for optimization of speed, resolution, and power. A programmable serial interface with one of three options (SPI, frame-sync slave, or frame-sync master) provides convenient interfacing across isolation barriers to microcontrollers or digital signal processors (DSPs).

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
ADS127L01 TQFP (32) 5.00 mm × 5.00 mm
  1. For all available packages, see the package option addendum at the end of the data sheet.

ADS127L01 Block Diagram

ADS127L01 Blockdiagram_sbas607.gif

ADC Frequency Spectrum

ADS127L01 fp_graph_sbas607.gif