The ADS1282-HT device is an extremely high-performance, single-chip analog-to-digital converter (ADC) with an integrated, low-noise programmable gain amplifier (PGA) and two-channel input multiplexer (MUX). The ADS1282-HT device is suitable for the demanding needs of energy exploration and seismic monitoring environments.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS1282-HT | CDIP SB (28) | 7.49 mm × 35.56 mm |
TSSOP (28) | 4.40 mm × 9.70 mm |
Changes from G Revision (May 2015) to H Revision
Changes from F Revision (August 2011) to G Revision
Changes from C Revision (August 2010) to D Revision
The converter uses a fourth-order, inherently stable, delta-sigma (ΔΣ) modulator that provides outstanding noise and linearity performance. The modulator is used either in conjunction with the on-chip digital filter, or can be bypassed for use with post processing filters.
The flexible input MUX provides an additional external input for measurement, as well as internal self-test connections. The PGA features outstanding low noise (5 nV/√Hz) and high input impedance, allowing easy interfacing to geophones and hydrophones over a wide range of gains.
The digital filter provides selectable data rates from 250 to 4000 samples per second (SPS). The high-pass filter (HPF) features an adjustable corner frequency. On-chip gain and offset scaling registers support system calibration.
The synchronization input (SYNC) can be used to synchronize the conversions of multiple ADS1282s. The SYNC input also accepts a clock input for continuous alignment of conversions from an external source.
Two operating modes allow optimization of noise and power. Together, the amplifier, modulator, and filter dissipate 30 mW. The ADS1282-SP is fully specified from –55°C to 210°C or from –55°C to 175°C for the PW package.
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | CDIP SB | TSSOP | ||
CLK | 1 | 1 | Digital input | Master clock input |
SCLK | 2 | 2 | Digital input | Serial clock input |
DRDY | 3 | 3 | Digital output | Data ready output: read data on falling edge |
DOUT | 4 | 4 | Digital output | Serial data output |
DIN | 5 | 5 | Digital input | Serial data input |
MCLK | 7 | 7 | Digital I/O | Modulator clock output; if in modulator mode: MCLK: Modulator clock output Otherwise, the pin is an unused input (must be tied). |
M1 | 8 | 8 | Digital I/O | Modulator data output 1; if in modulator mode: M1: Modulator data output 1 Otherwise, the pin is an unused input (must be tied). |
M0 | 9 | 9 | Digital I/O | Modulator data output 0; if in modulator mode: M0: Modulator data output 0 Otherwise, the pin is an unused input (must be tied). |
SYNC | 10 | 10 | Digital input | Synchronize input |
MFLAG | 11 | 11 | Digital output | Modulator Over-Range flag: 0 = normal, 1 = modulator over-range |
DGND | 6 | 6 | Digital ground | Digital ground, pin 12 is the key ground point |
12 | 12 | |||
27 | 25 | |||
29 | 27 | |||
CAPN | 13 | 13 | Analog | PGA outputs: Connect 10-nF capacitor from CAPP to CAPN |
CAPP | 14 | 14 | Analog | PGA outputs: Connect 10-nF capacitor from CAPP to CAPN |
AINP2 | 15 | 15 | Analog input | Positive analog input 2 |
AINN2 | 16 | 16 | Analog input | Negative analog input 2 |
AINP1 | 17 | 17 | Analog input | Positive analog input 1 |
AINN1 | 18 | 18 | Analog input | Negative analog input 1 |
AVDD | 19 | 19 | Analog supply | Positive analog power supply |
20 | ||||
AVSS | 21 | 20 | Analog supply | Negative analog power supply |
22 | ||||
VREFN | 23 | 21 | Analog input | Negative reference input |
VREFP | 24 | 22 | Analog input | Positive reference input |
PWDN | 25 | 23 | Digital input | Power-down input, active low |
RESET | 26 | 24 | Digital input | Reset input, active low |
DVDD | 28 | 26 | Digital supply | Digital power supply: 1.8 V to 3.3 V |
BYPAS | 30 | 28 | Analog | Sub-regulator output: Connect 1-μF capacitor to DGND |