ADS4249 Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC

1 Features

• Maximum Sample Rate: 250 MSPS
• Ultra-Low Power with Single 1.8-V Supply:
  • 560-mW Total Power at 250 MSPS
• High Dynamic Performance:
  • 80-dBc SFDR at 170 MHz
  • 71.7-dBFS SNR at 170 MHz
• Crosstalk: > 90 dB at 185 MHz
• Programmable Gain up to 6 dB for
  SNR/SFDR Trade-off
• DC Offset Correction
• Output Interface Options:
  • 1.8-V Parallel CMOS Interface
  • Double Data Rate (DDR) LVDS with Programmable Swing:
    • Standard Swing: 350 mV
    • Low Swing: 200 mV
• Supports Low Input Clock Amplitude
  Down to 200 mV_PP
• Package: 9-mm × 9-mm, 64-Pin VQFN Package

2 Applications

• Wireless Communications Infrastructure
• Software Defined Radios
• Power Amplifier Linearization

3 Description

The ADS4249 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance and consume extremely low power with a 1.8-V supply. This topology makes the ADS4249 well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS4249 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS and parallel CMOS digital output interfaces are available in a compact VQFN-64 PowerPAD™ package.

The device includes internal references and the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4249 is specified over the industrial temperature range (–40°C to 85°C).

1. For all available packages, see the orderable addendum at the end of the data sheet.

ADS4249 Block Diagram

4 Revision History

Changes from D Revision (May 2015) to E Revision

• Changed Pin Functions (LVDS Mode) table to comply with RGC Package (LVDS Mode) pin out diagramGo
• Changed Pin Functions (CMOS Mode) table to comply with RGC Package (CMOS Mode) pin out diagram Go
• Changed unit in last row of Clock Input, Input clock amplitude differential parameter to V_PP in Recommended Operating Conditions tableGo
• Added text reference for Table 5 Go

Changes from C Revision (July 2012) to D Revision

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from B Revision (September 2011) to C Revision

• Changed footnote 1 in CMOS Timings at Lower Sampling FrequenciesGo
• Changed conditions for ADS4249 Typical Characteristics sectionGo
• Changed register D5h bit names of bits D7, D4, D3, and D0 in Table 10Go
• Changed register address D8 to DB in Table 10Go
• Changed register address D5h to match change in Table 10Go
• Changed register address DB to match change in Table 10Go

Changes from A Revision (September 2011) to B Revision

• Changed document status to Production DataGo
• Changed AC power-supply rejection ratio parameter test condition in ADS4249 Electrical Characteristics tableGo

5 ADS424x, ADS422x Family Comparison⁽¹⁾