SBAS558C December   2012  – December 2015 ADS42B49

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 ADS424x and ADS422x Family Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics: ADS42B49 (250 MSPS)
    6. 8.6  Electrical Characteristics: General
    7. 8.7  Digital Characteristics
    8. 8.8  Timing Requirements: LVDS and CMOS Modes
    9. 8.9  Serial Interface Timing Characteristics
    10. 8.10 Reset Timing (Only When Serial Interface is Used)
    11. 8.11 LVDS Timings at Lower Sampling Frequencies
    12. 8.12 CMOS Timings at Lower Sampling Frequencies
    13. 8.13 Typical Characteristics
      1. 8.13.1 ADS42B49
      2. 8.13.2 Contour
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Migrating from the ADS62P49 and ADS4249
      2. 10.3.2 Digital Functions
      3. 10.3.3 Gain for SFDR and SNR Trade-Off
      4. 10.3.4 Offset Correction
    4. 10.4 Device Functional Modes
      1. 10.4.1 Power-Down
        1. 10.4.1.1 Global Power-Down
        2. 10.4.1.2 Channel Standby
        3. 10.4.1.3 Input Clock Stop
      2. 10.4.2 Digital Output Information
        1. 10.4.2.1 Output Interface
        2. 10.4.2.2 DDR LVDS Outputs
        3. 10.4.2.3 LVDS Buffer
        4. 10.4.2.4 Parallel CMOS Interface
        5. 10.4.2.5 CMOS Interface Power Dissipation
        6. 10.4.2.6 Multiplexed Mode of Operation
        7. 10.4.2.7 Output Data Format
      3. 10.4.3 Parallel Configuration Details
    5. 10.5 Programming
      1. 10.5.1 Parallel Configuration Only
      2. 10.5.2 Serial Interface Configuration Only
      3. 10.5.3 Using Both Serial Interface and Parallel Controls
      4. 10.5.4 Serial Interface Details
        1. 10.5.4.1 Register Initialization
        2. 10.5.4.2 Serial Register Readout
    6. 10.6 Register Maps
      1. 10.6.1 Register Description
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 Driving Circuit
        1. 11.1.1.1 Drive Circuit Requirements
      2. 11.1.2 Clock Input
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Analog Input
        2. 11.2.2.2 Clock Driver
        3. 11.2.2.3 Digital Interface
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
    1. 12.1 Using DC/DC Power Supplies
    2. 12.2 Power Supply Bypassing
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Grounding
      2. 13.1.2 Supply Decoupling
      3. 13.1.3 Exposed Pad
      4. 13.1.4 Routing Analog Inputs
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Device Nomenclature
    2. 14.2 Documentation Support
      1. 14.2.1 Related Documentation
    3. 14.3 Community Resources
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Maximum Sample Rate: 250 MSPS
  • Ultralow Power:
    • 850-mW Total Power at 250 MSPS
  • Integrated Analog Input Buffer:
    • Input Capacitance: 2.2 pF at 170 MHz
    • Input Resistance: 1.1 kΩ at 170 MHz
  • High Dynamic Performance:
    • 85-dBc SFDR at 170 MHz
    • 70.7-dBFS SNR at 170 MHz
  • Crosstalk: > 85 dB at 185 MHz
  • Programmable Gain Up to 6 dB for
    SNR and SFDR Trade-off
  • DC Offset Correction
  • Output Interface Options:
    • 1.8-V Parallel CMOS Interface
    • Double Data Rate (DDR) LVDS with Programmable Swing:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
  • Supports Low Input Clock Amplitude
    Down to 200 mVPP
  • Package: 9.00 mm × 9.00 mm, 64-Pin Quad Flat No-Lead (VQFN) Package

2 Applications

  • Wireless Communications Infrastructure
  • Software-Defined Radio
  • Power Amplifier Linearization

3 Description

The ADS42B49 is an ultralow-power dual-channel, 14-bit analog-to-digital converter (ADC) featuring integrated analog input buffers. It uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power. The presence of analog input buffers makes this device easy to drive and helps achieve high performance over a wide frequency range. The ADS42B49 is well-suited for multi-carrier, wide bandwidth communications applications.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
ADS42B49 VQFN(64) 9.00 mm × 9.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Block Diagram

ADS42B49 FBD_SBAS558.gif