The ADS42JB46 is a high-linearity, dual-channel, 14-bit, 160-MSPS, analog-to-digital converter (ADC). This device supports the JESD204B serial interface with data rates up to 3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy, thus making driving analog inputs up to very high input frequencies easy. A sampling clock divider allows more flexibility for system clock architecture design. The device employs internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS42JB46 | VQFN (64) | 9.00 mm × 9.00 mm |
Changes from A Revision (August 2013) to B Revision
Changes from * Revision (July 2013) to A Revision
INTERFACE OPTION | 14-BIT, 160 MSPS |
14-BIT, 250 MSPS |
16-BIT, 250 MSPS |
---|---|---|---|
DDR, QDR LVDS | — | ADS42LB49 | ADS42LB69 |
JESD204B | ADS42JB46 | ADS42JB46 | ADS42JB69 |
PIN | I/O | FUNCTION | DESCRIPTION | |
---|---|---|---|---|
NAME | NO. | |||
AGND | 12, 15, 19, 20, 23, 26, 28, 34, 37 | I | Supply | Analog ground |
AVDD | 11, 16, 18, 22, 27, 31, 33, 38, 40 | I | Supply | 1.8-V analog power supply |
AVDD3V | 17, 32 | I | Supply | 3.3-V analog supply for analog buffer |
CLKINM | 24 | I | Clock | Differential ADC clock input (negative) |
CLKINP | 25 | I | Clock | Differential ADC clock input (positive) |
CTRL1 | 39 | I | Control | Power-down control with an internal 150-kΩ pull-down resistor |
CTRL2 | 10 | I | Control | Power-down control with an internal 150-kΩ pull-down resistor |
DA0M | 53 | O | Interface | JESD204B serial data output for channel A, lane 0 (negative) |
DA0P | 54 | O | Interface | JESD204B serial data output for channel A, lane 0 (positive) |
DA1M | 51 | O | Interface | JESD204B serial data output for channel A, lane 1 (negative) |
DA1P | 52 | O | Interface | JESD204B serial data output for channel A, lane 1 (positive) |
DB0M | 57 | O | Interface | JESD204B serial data output for channel B, lane 0 (negative) |
DB0P | 56 | O | Interface | JESD204B serial data output for channel B, lane 0 (positive) |
DB1M | 59 | O | Interface | JESD204B serial data output for channel B, lane 1 (negative) |
DB1P | 58 | O | Interface | JESD204B serial data output for channel B, lane 1 (positive) |
DGND | 1, 3, 46, 48, 50, 63 | I | Supply | Digital ground |
DRVDD | 2, 7, 47, 49, 60, 64 | I | Supply | Digital 1.8-V power supply |
INAM | 35 | I | Input | Differential analog input for channel A (negative) |
INAP | 36 | I | Input | Differential analog input for channel A (positive) |
INBM | 14 | I | Input | Differential analog input for channel B (negative) |
INBP | 13 | I | Input | Differential analog input for channel B (positive) |
IOVDD | 55 | I | Supply | Digital 1.8-V power supply for the JESD204B transmitter |
MODE | 4 | I | Control | Connect to GND |
OVRA | 61 | O | Interface | Overrange indication for channel A in CMOS output format |
OVRB | 62 | O | Interface | Overrange indication for channel B in CMOS output format |
PDN_GBL | 6 | I | Control | Global power-down. Active high with an internal 150-kΩ pull-down resistor. |
RESET | 44 | I | Control | Hardware reset; active high. This pin has an internal 150-kΩ pull-down resistor. |
SCLK | 43 | I | Control | Serial interface clock input. This pin has an internal 150-kΩ pull-down resistor. |
SDATA | 42 | I | Control | Serial interface data input. This pin has an internal 150-kΩ pull-down resistor. |
SDOUT | 45 | O | Control | Serial interface data output |
SEN | 41 | I | Control | Serial interface enable. This pin has an internal 150-kΩ pull-up resistor. |
STBY | 5 | I | Control | Standby. Active high with an internal 150-kΩ pull-down resistor. |
SYNC~M | 8 | I | Interface | Synchronization input for JESD204B port (negative) |
SYNC~P | 9 | I | Interface | Synchronization input for JESD204B port (positive) |
SYSREFM | 30 | I | Clock | External SYSREF input, subclass 1 (negative) |
SYSREFP | 29 | I | Clock | External SYSREF input, subclass 1 (positive) |
VCM | 21 | O | Output | 1.9-V common-mode output voltage for analog inputs |
Thermal Pad | 65 | GND | Ground | Connect to ground plane |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage | AVDD3V | –0.3 | 3.6 | V |
AVDD | –0.3 | 2.1 | V | |
DRVDD | –0.3 | 2.1 | V | |
IOVDD | –0.3 | 2.1 | V | |
Voltage between AGND and DGND | –0.3 | 0.3 | V | |
Voltage applied to input pins | INAP, INBP, INAM, INBM | –0.3 | 3 | V |
CLKINP, CLKINM | –0.3 | minimum (2.1, AVDD + 0.3) | V | |
SYNC~P, SYNC~M | –0.3 | minimum (2.1, AVDD + 0.3) | V | |
SYSREFP, SYSREFM | –0.3 | minimum (2.1, AVDD + 0.3) | V | |
SCLK, SEN, SDATA, RESET, PDN_GBL, CTRL1, CTRL2, STBY, MODE | –0.3 | 3.9 | V | |
Temperature | Operating free-air, TA | –40 | 85 | °C |
Operating junction, TJ | 125 | °C | ||
Storage, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
SUPPLIES | ||||||
AVDD | Analog supply voltage | 1.7 | 1.8 | 1.9 | V | |
AVDD3V | Analog buffer supply voltage | 3.15 | 3.3 | 3.45 | V | |
DRVDD | Digital supply voltage | 1.7 | 1.8 | 1.9 | V | |
IOVDD | Output buffer supply voltage | 1.7 | 1.8 | 1.9 | V | |
ANALOG INPUTS | ||||||
VID | Differential input voltage range | Default after reset | 2 | VPP | ||
Register programmable(1) | 2.5 | VPP | ||||
VICR | Input common-mode voltage | VCM ± 0.025 | V | |||
Maximum analog input frequency with 2.5-VPP input amplitude | 250 | MHz | ||||
Maximum analog input frequency with 2-VPP input amplitude | 400 | MHz | ||||
CLOCK INPUT | ||||||
Input clock sample rate | 10x mode | 60 | 160 | MSPS | ||
20x mode | 40 | 156.25 | MSPS | |||
Input clock amplitude differential (VCLKP – VCLKM) |
Sine wave, ac-coupled | 0.3(2) | 1.5 | VPP | ||
LVPECL, ac-coupled | 1.6 | VPP | ||||
LVDS, ac-coupled | 0.7 | VPP | ||||
LVCMOS, single-ended, ac-coupled | 1.5 | V | ||||
Input clock duty cycle | 35% | 50% | 65% | |||
DIGITAL OUTPUTS | ||||||
CLOAD | Maximum external load capacitance from each output pin to DRGND | 3.3 | pF | |||
RLOAD | Single-ended load resistance | +50 | Ω | |||
TA | Operating free-air temperature | –40 | 85 | °C |
THERMAL METRIC(1) | ADS42JB46 | UNIT | |
---|---|---|---|
RGC (QFN) | |||
64 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 22.9 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 7.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 2.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.1 | °C/W |
ψJB | Junction-to-board characterization parameter | 2.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 0.2 | °C/W |
PARAMETER | TEST CONDITIONS | 2-VPP FULL-SCALE | 2.5-VPP FULL-SCALE | UNIT | |||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
SNR | Signal-to-noise ratio | fIN = 10 MHz | 73.7 | 75.2 | dBFS | ||||
fIN = 70 MHz | 73.5 | 74.9 | dBFS | ||||||
fIN = 170 MHz | 69.5 | 72.9 | 74.2 | dBFS | |||||
fIN = 230 MHz | 72.3 | 73.3 | dBFS | ||||||
SINAD | Signal-to-noise and distortion ratio | fIN = 10 MHz | 73.5 | 75.1 | dBFS | ||||
fIN = 70 MHz | 73.3 | 74.7 | dBFS | ||||||
fIN = 170 MHz | 68.5 | 72.8 | 73.6 | dBFS | |||||
fIN = 230 MHz | 72 | 72.8 | dBFS | ||||||
SFDR | Spurious-free dynamic range (including second and third harmonic distortion) |
fIN = 10 MHz | 96 | 92 | dBc | ||||
fIN = 70 MHz | 94 | 90 | dBc | ||||||
fIN = 170 MHz | 79 | 90 | 84 | dBc | |||||
fIN = 230 MHz | 86 | 83 | dBc | ||||||
THD | Total harmonic distortion | fIN = 10 MHz | 93 | 90 | dBc | ||||
fIN = 70 MHz | 91 | 88 | dBc | ||||||
fIN = 170 MHz | 76 | 87 | 82 | dBc | |||||
fIN = 230 MHz | 84 | 81 | dBc | ||||||
HD2 | 2nd-order harmonic distortion | fIN = 10 MHz | 96 | 95 | dBc | ||||
fIN = 70 MHz | 94 | 90 | dBc | ||||||
fIN = 170 MHz | 79 | 92 | 89 | dBc | |||||
fIN = 230 MHz | 88 | 86 | dBc | ||||||
HD3 | 3rd-order harmonic distortion | fIN = 10 MHz | 97 | 92 | dBc | ||||
fIN = 70 MHz | 96 | 94 | dBc | ||||||
fIN = 170 MHz | 79 | 90 | 84 | dBc | |||||
fIN = 230 MHz | 86 | 83 | dBc | ||||||
Worst spur (other than second and third harmonics) |
fIN = 10 MHz | 102 | 101 | dBc | |||||
fIN = 70 MHz | 102 | 100 | dBc | ||||||
fIN = 170 MHz | 87 | 100 | 95 | dBc | |||||
fIN = 230 MHz | 98 | 92 | dBc | ||||||
IMD | Two-tone intermodulation distortion | f1 = 46 MHz, f2 = 50 MHz, each tone at –7 dBFS |
97 | 95 | dBFS | ||||
f1 = 185 MHz, f2 = 190 MHz, each tone at –7 dBFS |
90 | 89 | dBFS | ||||||
Crosstalk | 20-MHz, full-scale signal on channel under observation; 170-MHz, full-scale signal on other channel |
100 | 100 | dB | |||||
Input overload recovery | Recovery to within 1% (of full-scale) for 6-dB overload with sine-wave input | 1 | 1 | Clock cycle | |||||
PSRR | AC power-supply rejection ratio | For a 90-mVPP signal on AVDD supply, up to 10 MHz | > 40 | > 40 | dB | ||||
ENOB | Effective number of bits | fIN = 170 MHz | 11.8 | 12 | LSBs | ||||
DNL | Differential nonlinearity | fIN = 170 MHz | ±0.4 | ±0.5 | LSBs | ||||
INL | Integrated nonlinearity | fIN = 170 MHz | ±0.75 | ±3 | ±0.9 | LSBs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG INPUTS | ||||||
VID | Differential input voltage range | Default (after reset) | 2 | VPP | ||
Register programmed(1) | 2.5 | VPP | ||||
Differential input resistance (at 170 MHz) | 1.2 | kΩ | ||||
Differential input capacitance (at 170 MHz) | 4 | pF | ||||
Analog input bandwidth | With 50-Ω source impedance and 50-Ω termination | 900 | MHz | |||
VCM | Common-mode output voltage | 1.9 | V | |||
VCM output current capability | 10 | mA | ||||
DC ACCURACY | ||||||
Offset error | –20 | 20 | mV | |||
EGREF | Gain error as a result of internal reference inaccuracy alone | –2 | 2 | %FS | ||
EGCHAN | Gain error of channel alone | –5 | %FS | |||
Temperature coefficient of EGCHAN | 0.01 | Δ%/°C | ||||
POWER SUPPLY | ||||||
IAVDD | Analog supply current | 90 | 130 | mA | ||
IAVDD3V | Analog buffer supply current | 234 | 330 | mA | ||
IDRVDD | Digital supply current | 174 | 207 | mA | ||
IOVDD | Output buffer supply current | 50-Ω external termination from pin to IOVDD, fIN = 2.5 MHz, 10x mode | 61 | 100 | mA | |
Analog power | 162 | mW | ||||
Analog buffer power | 772 | mW | ||||
Digital power | 313 | mW | ||||
Power consumption by output buffer | 50-Ω external termination from pin to IOVDD, fIN = 2.5 MHz, 10x mode | 109 | mW | |||
Total power | 1.36 | 1.64 | W | |||
Global power-down | 160 | mW |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
SAMPLE TIMING CHARACTERISTICS | ||||||||
Aperture delay | 0.4 | 0.7 | 1.1 | ns | ||||
Aperture delay matching | Between two channels on the same device | ±70 | ps | |||||
Between two devices at the same temperature and supply voltage | ±150 | ps | ||||||
Aperture jitter | 85 | fS rms | ||||||
Wake-up time | Time to valid data after exiting STANDBY mode | 50 | 200 | µs | ||||
Time to valid data after exiting global power-down | 250 | 1000 | µs | |||||
tSU_SYNC~ | Setup time for SYNC~ | Referenced to input clock rising edge | 400 | ps | ||||
tH_SYNC~ | Hold time for SYNC~ | Referenced to input clock rising edge | 100 | ps | ||||
tSU_SYSREF | Setup time for SYSREF | Referenced to input clock rising edge | 400 | ps | ||||
tH_SYSREF | Hold time for SYSREF | Referenced to input clock rising edge | 100 | ps | ||||
CML OUTPUT TIMING CHARACTERISTICS | ||||||||
Unit interval | 320 | 1667 | ps | |||||
Serial output data rate | 3.125 | Gbps | ||||||
TJitter | Total jitter | 1.6 Gbps (10x mode, fS = 160 MSPS) | 0.28 | P-PUI | ||||
3.125 Gbps (20x mode, fS = 156.25 MSPS) | 0.3 | P-PUI | ||||||
tR, tF | Data rise time, data fall time |
Rise and fall times are measured from 20% to 80%, differential output waveform, 600 Mbps ≤ bit rate ≤ 3.125 Gbps |
105 | ps |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DIGITAL INPUTS (RESET, SCLK, SEN, SDATA, PDN_GBL, STBY, CTRL1, CTRL2, MODE)(1) | ||||||
VIH | High-level input voltage | All digital inputs support 1.8-V and 3.3-V logic levels |
1.2 | V | ||
VIL | Low-level input voltage | All digital inputs support 1.8-V and 3.3-V logic levels |
0.4 | V | ||
IIH | High-level input current | SEN | 0 | µA | ||
RESET, SCLK, SDATA, PDN_GBL, STBY, CTRL1, CTRL2, MODE | 10 | µA | ||||
IIL | Low-level input current | SEN | 10 | µA | ||
RESET, SCLK, SDATA, PDN_GBL, STBY, CTRL1, CTRL2, MODE | 0 | µA | ||||
DIGITAL INPUTS (SYNC~P, SYNC~M, SYSREFP, SYSREFM) | ||||||
VIH | High-level input voltage | 1.3 | V | |||
VIL | Low-level input voltage | 0.5 | V | |||
VCM_DIG | Input common-mode voltage | 0.9 | V | |||
DIGITAL OUTPUTS (SDOUT, OVRA, OVRB) | ||||||
VOH | High-level output voltage | DRVDD – 0.1 | DRVDD | V | ||
VOL | Low-level output voltage | 0.1 | V | |||
DIGITAL OUTPUTS (JESD204B Interface: DA[0,1], DB[0,1])(2) | ||||||
VOH | High-level output voltage | IOVDD | V | |||
VOL | Low-level output voltage | IOVDD – 0.4 | V | |||
|VOD| | Output differential voltage | 0.4 | V | |||
VOCM | Output common-mode voltage | IOVDD – 0.2 | V | |||
Transmitter short-circuit current | Transmitter terminals shorted to any voltage between –0.25 V and 1.45 V | –100 | 100 | mA | ||
Single-ended output impedance | 50 | Ω | ||||
COUT | Output capacitance | Output capacitance inside the device, from either output to ground |
2 | pF |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
t1 | Power-on delay | Delay from AVDD and DRVDD power-up to active RESET pulse | 1 | ms | ||
t2 | Reset pulse width | Active RESET signal pulse width | 10 | ns | ||
1 | µs | |||||
t3 | Register write delay | Delay from RESET disable to SEN active | 100 | ns |
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
fSCLK | SCLK frequency (equal to 1 / tSCLK) | > dc | 20 | MHz | |
tSLOADS | SEN to SCLK setup time | 25 | ns | ||
tSLOADH | SCLK to SEN hold time | 25 | ns | ||
tDSU | SDIO setup time | 25 | ns | ||
tDH | SDIO hold time | 25 | ns |