• Menu
  • Product
  • Email
  • PDF
  • Order now

  • ADS5263 Quad Channel 16-Bit, 100-MSPS High-SNR ADC

    • SLAS760D May   2011  – November 2015 ADS5263

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • ADS5263 Quad Channel 16-Bit, 100-MSPS High-SNR ADC
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics, Dynamic Performance - 16-Bit ADC
    6. 7.6  Electrical Characteristics, General - 16-Bit ADC Mode
    7. 7.7  Electrical Characteristics, Dynamic Performance - 14-Bit ADC
    8. 7.8  Digital Characteristics
    9. 7.9  Timing Requirements
    10. 7.10 LVDS Timing at Lower Sampling Frequencies - 2 Wire, 8× Serialization
    11. 7.11 LVDS Timing for 1 Wire 16× Serialization
    12. 7.12 LVDS Timing for 2 Wire, 7× Serialization
    13. 7.13 LVDS Timing for 1 Wire, 14× Serialization
    14. 7.14 Serial Interface Timing Requirements
    15. 7.15 Reset Switching Characteristics
    16. 7.16 Typical Characteristics
      1. 7.16.1 Typical Characteristic - 16-Bit ADC Mode
      2. 7.16.2 Typical Characteristic - 14-Bit ADC Mode
      3. 7.16.3 Typical Characteristics - Common Plots
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital Processing Blocks
      2. 8.3.2 Digital Gain
      3. 8.3.3 Digital Filter
      4. 8.3.4 Custom Filter Coefficients
        1. 8.3.4.1 Custom Filter Without Decimation
      5. 8.3.5 Digital Averaging
      6. 8.3.6 Performance with Digital Processing Blocks
        1. 8.3.6.1 18-Bit Data Output with Digital Processing
      7. 8.3.7 Flexible Mapping o Channel Data to LVDS Outputs
      8. 8.3.8 Output LVDS Interface
      9. 8.3.9 Programmable LCLK Phase
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
      2. 8.4.2 Serial Register Readout
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
      2. 8.5.2 Register Initialization
    6. 8.6 Register Maps
      1. 8.6.1 Default State After Reset
      2. 8.6.2 Description of Serial Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Input
        1. 9.1.1.1 Drive Circuit Requirements
      2. 9.1.2 Large and Small Signal Input Bandwidth
      3. 9.1.3 Clamp Function For CCD Signals
        1. 9.1.3.1 Differential Input Drive
        2. 9.1.3.2 Clamp Operation
        3. 9.1.3.3 Synchronization to External CCD Timing
      4. 9.1.4 Low-Frequency Noise Suppression
      5. 9.1.5 External Reference Mode
    2. 9.2 Typical Applications
      1. 9.2.1 Driving Circuit Design: Low Input Frequencies (< 50 MHz)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Driving Circuit Design: Input Frequencies > 50 MHz
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Definition of Specifications
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging
      1. 13.1.1 Exposed Pad
      2. 13.1.2 Non-Magnetic Package
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • RGC|64
    • MPQF125F
Thermal pad, mechanical data (Package|Pins)
  • RGC|64
    • QFND123N
Orderable Information
  • slas760d_oa
  • slas760d_pm
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

ADS5263 Quad Channel 16-Bit, 100-MSPS High-SNR ADC

1 Features

  • Maximum Sample Rate: 100 MSPS
  • Programmable Device Resolution
    • Quad-Channel, 16-Bit, High-SNR Mode
    • Quad-Channel, 14-Bit, Low-Power Mode
  • 16-Bit High-SNR Mode
    • 1.4 W Total Power at 100 MSPS
      • 355 mW / Channel
    • 4 Vpp Full-scale Input
    • 85-dBFS SNR at fin = 3 MHz, 100 MSPS
  • 14-Bit Low-Power Mode
    • 785 mW Total Power at 100 MSPS
      • 195 mW/Channel
    • 2-Vpp Full-Scale Input
    • 74-dBFS SNR at fin = 10 MHz
    • Integrated Clamp (for interfacing to CCD sensors)
  • Low-Frequency Noise Suppression
  • Digital Processing Block
    • Programmable FIR Decimation Filters
    • Programmable Digital Gain: 0 dB to 12 dB
    • 2- or 4-Channel Averaging
  • Programmable Mapping Between ADC Input Channels and LVDS Output Pins—Eases Board Design
  • Variety of Test Patterns to Verify Data Capture by FPGA/Receiver
  • Serialized LVDS Outputs
  • Internal and External References
  • 3.3-V Analog Supply
  • 1.8-V Digital Supply
  • Recovers From 6-dB Overload Within 1 Clock Cycle
  • Package:
    • 9-mm × 9-mm 64-Pin QFN
    • Non-Magnetic Package Option for MRI Systems
  • CMOS Technology

2 Applications

  • Medical Imaging – MRI
  • Spectroscopy
  • CCD Imaging

3 Description

Using CMOS process technology and innovative circuit techniques, the ADS5263 is designed to operate at low power and give very high SNR performance with a 4-Vpp full-scale input. Using a low-noise 16-bit front-end stage followed by a 14-bit ADC, the device gives 85-dBFS SNR up to 10 MHz and better than 80-dBFS SNR up to 30 MHz.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
ADS5263 VQFN (64) 9.00 mm × 9.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

ADS5263 Block Diagram

ADS5263 FBD_SLAS760.gif

4 Revision History

Changes from C Revision (January 2013) to D Revision

  • Added Register 57 in Register Maps Go
  • Added Register CB in Register Maps Go
  • Added Typical Applications sectionGo
  • Added Layout section Go
  • Deleted Ordering Information table. See POA at the end of the data sheet. Go

Changes from B Revision (October 2011) to C Revision

  • Changed Pin 54 From: REFB To: NCGo
  • Changed Pin 55 From: REFC To: NCGo
  • Changed the VCM Pin description To: "Internal reference mode: Outputs the common-mode voltage (1.5 V) that can be used externally to bias the analog input External reference mode: Apply voltage input that sets the reference for ADC operation." From: "Outputs the common-mode voltage (1.5 V) that can be used externally to bias the analog input pins."Go
  • Added "Idle channel noise" To SNRGo
  • Added "Idle channel noise" To LSBGo
  • Changed the INL values- 100 MSPS From: TYP = ±2.2 To: ±5, Added MAX = ±12Go
  • to Changed the INL values- 80 MSPS From: TYP = ±2.2 To: ±5Go
  • Added From: VCM common-mode output voltage To: VCM common-mode output voltage, Internal reference mode Go
  • Added From: VCM output current capability To: VCM output current capability, Internal reference modeGo
  • Added From: VCM input voltage To: VCM input current, external reference modeGo
  • Added VCM input current, external reference mode Typical value - 80 MSPS of 0.5Go
  • Changed EGREF - 100 MSPS MIN value From: ±2.5 To: ±1Go
  • Added Temperature Coefficient to EGREF Go
  • Added Temperature Coefficient to EGCHANGo
  • Changed SNR fin = 5 MHz MIN value From: 68.8 To: to 67.5Go
  • Added tA Aperture delay to the Timing Requirements TableGo
  • Changed From: 2 WIRE, 16× SERIALIZATION To: 2 WIRE, 8× SERIALIZATIONGo
  • Added 100 MSPS to the SAMPLING FREQUENCY, MSPS column of LVDS Timing at Lower Sampling Frequencies - 2 Wire, 8× SerializationGo
  • Changed to 8x from 16xGo
  • Changed LVDS Timing for 2 Wire, 7× Serialization title From: LVDS Timing for 2 Wire, 14× Serialization To: LVDS Timing for 2 Wire, 7× SerializationGo
  • Changed the Digital Filter SectionGo
  • Changed Table 9 Description From: Reference voltage must be forced on REFT and REFB pins To: Apply voltage on VCM pin to set the references for ADC operationGo
  • Table 10 Added: <EN_HIGH_ADDRS> as bit D4. Added: Register 0x09 to Serial Register Ma;Go
  • Table 10 Added: Register bit EXT_REF_VCM. Added: D12 <18x SERIALIZATION>Go
  • Table 10 Added: new register entries from Address 5A to 89. Added: new register F0Go
  • Added D4 <EN_HIGH_ADDRS>Go
  • Added Added register description table (D10 <EN_CLAMP>) for register 0x09Go
  • Added description for register EXT_REF_VCM Go
  • Added Description for <EN_REG_42>, <PHASE_DDR> and EXT_REF_VCMGo
  • Added Decsription for 18b SERIALIZATIONGo
  • Changed D11, D10, and D5 To: SERIALIZATION From: SERIAL'NGo
  • Changed the register for A7-A0 IN HEXGo
  • Added description for register F0 for A7–A0 IN HEXGo
  • Replaced the Clamp Function section with the Clamp Functon for CCD Signals sectionGo
  • Deleted Figure - CCD Sensor ConnectionsGo
  • Added External Reference ModeGo

Changes from A Revision (August 2011) to B Revision

  • Added new Figure below Figure 16Go
  • Added new Figure below Figure 22 (now Figure 24)Go
  • Added new section below Digital Averaging titled: Performance with Didgital Processing BlocksGo
  • Added listitem 6. to the OUTPUT LVDS INTERFACE sectionGo
  • Added Added new figure in section Output LVDS Interface (Figure 55)Go
  • Added new section after Output LVDS Interface titled: Programmable LCLK Phase, also 2 new figures added.Go
  • Added register 42 between register 38 and register 45 Go
  • Added new figure 52 in Large and Smll Signal Input Bandwidth sectionGo

Changes from * Revision (May 2011) to A Revision

  • Added "Non-Magnetic Package Option for MRI Systems" to FeaturesGo
  • Changed Features List Item - From: 1.35 W Total Power at 100 MSPS To: 1.4 W Total Power at 100 MSPSGo
  • Changed Features List Item - From: 338 mW / Channel To: 355 mW / ChannelGo
  • Changed the CLOCK INPUT values in the ROC tableGo
  • Changed the ELECTRICAL CHARACTERISTICS, DYNAMIC PERFORMANCE – 16-BIT ADC tableGo
  • Changed the ELECTRICAL CHARACTERISTICS, GENERAL – 16-BIT ADC MODE tableGo
  • Added the ELECTRICAL CHARACTERISTICS, DYNAMIC PERFORMANCE – 14-BIT ADC tableGo
  • Changed the values in DIGITAL OUTPUTS – LVDS INTERFACEGo
  • Added LVDS Timing for 1 Wire 16× Serialization, LVDS Timing for 2 Wire, 7× Serialization, and LVDS Timing for 1 Wire, 14× SerializationGo
  • Added Figure 25, Figure 26, and Figure 27Go
  • Added section - Large and Small Signal Input BandwidthGo
  • Added Section - Board Design ConsiderationsGo
  • Added Package Marking ADS5263NM and Ordering Number ADS5263IRGC-NMGo
  • Added Section - DEFINITION OF SPECIFICATIONSGo
  • Added Section - PackagingGo

5 Description (continued)

ADS5263 has a 14-bit low power mode, where it operates as a quad-channel 14-bit ADC. The 16-bit front-end stage is powered down and the part consumes almost half the power, compared to the 16-bit mode. The 14-bit mode supports a 2-Vpp full-scale input signal, with typical 74-dBFS SNR. The ADS5263 can be dynamically switched between the two resolution modes. This allows systems to use the same part in a high-resolution, high-power mode or a low-resolution, low-power mode.

The device also has a digital processing block that integrates several commonly used digital functions, such as digital gain (up to 12 dB). It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This makes it very useful for narrow-band applications, where the filters can be used to improve SNR and knock-off harmonics, while at the same time reducing the output data rate.

The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR. A very unique feature is the programmable mapper module that allows flexible mapping between the input channels and the LVDS output pins. This helps to greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers. Specification of device is over industrial temperature range of –40°C to 85°C.

6 Pin Configuration and Functions

QFN Package
64-Pin With Thermal Pad
Top View
ADS5263 P0056-19_LAS760.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
ADCLKM 24 O LVDS frame clock (1X) – negative output
ADCLKP 23 O LVDS frame clock (1X) – positive output
AGND 3, 6, 9, 37,
40, 43, 46		 I Analog ground
AVDD 50, 57, 60 I Analog power supply, 3.3 V
CLKM 59 I Negative differential clock input. For single-ended clock, tie CLKM to ground.
CLKP 58 I Positive differential clock input
CS 61 I Serial interface enable input, active LOW. The pin has an internal 300-kΩ pulldown resistor to ground
IN1A_P, IN1A_M 1, 2 I Differential analog input for channel 1, 16 bit ADC
IN1B_P, IN1B_M 4, 5 I Differential analog input for channel 1, 14 bit ADC
IN2A_P, IN2A_M 7, 8 I Differential analog input for channel 2, 16 bit ADC
IN2B_P, IN2B_M 10, 11 I Differential analog input for channel 2, 14 bit ADC
IN3A_P, IN3A_M 41, 42 I Differential analog input for channel 3, 16 bit ADC
IN3B_P, IN3B_M 38, 39 I Differential analog input for channel 3, 14 bit ADC
IN4A_P, IN4A_M 47, 48 I Differential analog input for channel 4, 16 bit ADC
IN4B_P, IN4B_M 44, 45 I Differential analog input for channel 4, 14 bit ADC
INT/EXT 56 I Internal/external reference mode select input
Logic HIGH –internal reference
Logic LOW – external reference
ISET 51 I Bias pin – 56.2 kΩ resistor (1% tolerance value) to ground
LCLKM 26 O LVDS bit clock (8X) – negative output
LCLKP 25 O LVDS bit clock (8X) – positive output
LGND 12, 14, 36 I Digital ground
LVDD 35 I Digital and I/O power supply, 1.8 V
OUT1P, OUT1M 15, 16 O Wire 1, channel 1 LVDS differential output
OUT2P, OUT2M 17, 18 O Wire 2, channel 1 LVDS differential output
OUT3P, OUT3M 19, 20 O Wire 1, channel 2, LVDS differential output
OUT4P, OUT4M 21, 22 O Wire 2, channel 2 LVDS differential output
OUT5P, OUT5M 27, 28 O Wire 1, channel 3 LVDS differential output
OUT6P, OUT6M 29, 30 O Wire 2, channel 3 LVDS differential output
OUT7P, OUT7M 31, 32 O Wire 1, channel 4 LVDS differential output
OUT8P, OUT8M 33, 34 O Wire 2, channel 4 LVDS differential output
PD 13 I Power-down input
NC 54, 55 Do not connect
RESET 64 I Serial interface RESET input, active LOW.
When using the serial interface mode, the user must initialize internal registers through hardware RESET by applying a low-going pulse on this pin or by using software reset option. See the Serial Interface section.
SCLK 63 I Serial interface clock input. The pin has an internal 300-kΩ pulldown resistor.
SDATA 62 I Serial interface data input. The pin has an internal 300-kΩ pulldown resistor.
SDOUT 52 O Serial register readout
This pin is in the high-impedance state after reset. When the <READOUT> bit is set, the SDOUT pin becomes active. This is a CMOS digital output running from the AVDD supply.
SYNC 49 I Input signal to synchronize channels and chips when used with reduced output data rates
Alternate function: Clamp signal input (14-bit ADC mode only)
VCM 53 IO Internal reference mode: Outputs the common-mode voltage (1.5 V) that can be used externally to bias the analog input.
External reference mode: Apply voltage input that sets the reference for ADC operation.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, AVDD –0.3 3.9 V
Supply voltage, LVDD –0.3 2.2 V
Voltage between AGND and DRGND –0.3 0.3 V
Voltage applied to analog input pins – INP_A, INM_A, INP_B, INM_B –0.3 minimum (3.6, AVDD + 0.3 V) V
Voltage applied to input pins – CLKP, CLKM, RESET, SCLK, SDATA, CSZ –0.3 AVDD + 0.3 V
Voltage applied to reference input pins –0.3 2.8 V
Operating free-air temperature, TA –40 85 °C
Operating junction temperature, TJ 125 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
SUPPLIES
AVDD Analog supply voltage 3 3.3 3.6 V
LVDD Digital supply voltage 1.7 1.8 1.9 V
ANALOG INPUTS
Differential input voltage 16-bit ADC mode 4 VPP
14-bit ADC mode 2 VPP
Input common-mode voltage 1.5 ±0.1 V
Maximum analog input frequency 4-Vpp input amplitude, 16-bit ADC mode 70 MHz
2-Vpp input amplitude, 16-bit ADC mode 140
CLOCK INPUT
Input clock sample rate 10 100 MSPS
Input clock amplitude differential
(VCLKP-VCLKM)		 Sine wave, ac-coupled 0.2 1.5 VPP
LVPECL, ac-coupled 0.2 1.6 VPP
LVDS, ac-coupled 0.2 0.7 VPP
LVCMOS, single-ended, ac-coupled 3.3 V
Input clock duty cycle 35% 50% 65%
DIGITAL OUTPUTS
CLOAD Maximum external load capacitance from each output pin to DRGND 5 pF
RLOAD Differential load resistance between the LVDS output pairs (LVDS mode) 100 Ω
Operating free-air temperature, TA –40 85 °C

7.4 Thermal Information

THERMAL METRIC(1) ADS5263 UNIT
RGC (VQFN)
64 PINS
RθJA Junction-to-ambient thermal resistance 20.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 6.1 °C/W
RθJB Junction-to-board thermal resistance 2.7 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 2.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics, Dynamic Performance – 16-Bit ADC

Typical values are at 25°C, AVDD = 3.3V, LVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input (unless otherwise noted); MIN and MAX values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, LVDD = 1.8 V
PARAMETERS TEST CONDITIONS 100 MSPS 80 MSPS UNIT
MIN TYP MAX MIN TYP MAX
SNR
Idle channel noise		 With inputs tied to common-mode VCM 87.5 87.5 dBFS
LSB
Idle channel noise		 With inputs tied to common-mode VCM 0.98 0.98 rms
SNR
Signal-to-noise ratio		 fin = 5 MHz at 25°C 81 84.5 85.5 dBFS
fin = 5 MHz across temperature 80
fin = 10 MHz 84.6 85.3
fin = 30 MHz 82.7 83.1
fin = 65 MHz 78.9 79.4
SINAD
Signal-to-noise and distortion ratio		 fin = 5 MHz 76.6 78.2 78.8 dBFS
fin = 10 MHz 77.5 79
finn = 30 MHz 74.8 76
fin = 65 MHz 71.6 72.5
ENOB
Effective number of bits		 fin = 5 MHz 12.7 12.8 LSB
DNL
Differential non-linearity		 fin = 5 MHz ±0.1 ±0.1 LSB
INL
Integrated non-linearity		 fin = 5 MHz Changed the INL values 100 MSPS From: TYP = ±2.2 To: ±5, Added MAX = ±12 ±5 ±12 ±5 LSB
SFDR
Spurious-free dynamic range		 fin = 5 MHz 73.5 80 80 dBc
fin = 10 MHz 80 81
fin = 30 MHz 76 77
fin = 65 MHz 74 75
THD
Total harominc distortion		 fin = 5 MHz 72.5 78 78.8 dBc
fin = 10 MHz 77.4 79.2
fin = 30 MHz 74.5 76
fin = 65 MHz 71.4 72.4
HD2
Second harmonic Distortion		 fin = 5 MHz 73.5 83.5 85 dBc
fin = 10 MHz 81 84
fin = 30 MHz 80 83
fin = 65 MHz 75 76
HD3
Third harmonic distortion		 fin = 5 MHz 73.5 80 80 dBc
fin = 10 MHz 80 81
fin = 30 MHz 75 77
fin = 65 MHz 74 75
Worst Spur
Excluding HD2, HD3		 fin = 5 MHz 80 90 dBc
fin = 10 MHz 85 90
finn = 30 MHz 85 88
fin = 65 MHz 82 86
IMD
2-tone intermodulation distortion		 f1 = 8 MHz, f2 = 10 MHZ, each tone at –7 dBFS 92 92 dBFS
Input overload recovery Recovery to within 1% (of final value) for 6-dB overload with sine wave input 1 1 clock cyles
PSRR
AC power supply rejection ratio		 For 50 mV signal on AVDD supply, up to 1 MHz ripple frequency 30 30 dB

7.6 Electrical Characteristics, General – 16-Bit ADC Mode

Typical values are at 25°C, AVDD = 3.3V, LVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input (unless otherwise noted); MIN and MAX values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, LVDD = 1.8V
PARAMETERS 100 MSPS 80 MSPS UNIT
MIN TYP MAX MIN TYP MAX
ANALOG INPUT
Differential input voltage range (0-dB gain) 4 4 Vpp
Differential input resistance (at dc) 2.5 2.5 kΩ
Differential input capacitance 12 12 pF
Analog input bandwidth 700 700 MHz
Analog input common-mode current (per input pin) 8 8 µA/MSPS
VCM common-mode output voltage, Internal reference mode 1.5 1.5 V
VCM output current capability, Internal reference mode 3 3 mA
VCM input voltage, external reference mode 1.45 1.5 1.55 1.45 1.5 1.55 V
VCM input current, external reference mode 0.5 0.5 mA
DC ACCURACY
Offset error ±10 ±30 ±10 mV
EGREF Gain error due to internal reference inaccuracy alone ±1 ±0.5 1 ±0.5 % FS
EGREF
Temperature Coefficient		 Internal reference mode 0.002 0.002 Δ%/°C
External l reference mode 0.001 0.001 Δ%/°C
EGCHAN Gain error of channel alone 1 1 % FS
EGCHAN
Temperature Coefficient		 0.002 0.002 Δ%/°C
Gain matching 0.5% 0.5%
POWER SUPPLY
IAVDD Analog supply current 370 390 290 mA
ILVDD Digital and output buffer supply current with 100-Ω external LVDS termination 110 150 100 mA
Analog power 1.22 0.96 W
Digital power 0.2 0.18 W
Global power down 63 110 63 mW
Standby 208 250 208 mW

7.7 Electrical Characteristics, Dynamic Performance – 14-Bit ADC

Typical values are at 25°C, AVDD = 3.3V, LVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input (unless otherwise noted); MIN and MAX values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, LVDD = 1.8 V
PARAMETERS TEST CONDITIONS 100 MSPS UNIT
MIN TYP MAX
SNR
Signal-to-noise ratio		 fin = 5 MHz 67.5 74 dBFS
finv = 30 MHz 73
fin = 65 MHz 71.3
SINAD
Signal-to-noise and distortion ratio		 fin = 5 MHz 65.8 73.5 dBFS
fin = 30 MHz 71.9
finn = 65 MHz 70.3
SFDR
Spurious-free dynamic range		 fin = 5 MHz 71.8 85 dBc
fin = 30 MHz 81
fin = 65 MHz 78
THD
Total harmonic distortion		 fin = 5 MHz 69 83.5 dBc
fin = 30 MHz 78
fin = 65 MHz 76.5
HD2
Second harmonic Distortion		 fin = 5 MHz 71.8 92 dBc
fin = 30 MHz 84
fin = 65 MHz 80
HD3
Third harmonic distortion		 fin = 5 MHz 71.8 85 dBc
fin = 30 MHz 81
fin = 65 MHz 78

7.8 Digital Characteristics

The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = 3.3V, LVDD = 1.8V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS – RESET, SCLK, SDATA, CS, PDN, SYNC, INT/EXT
VIH High-level input voltage All digital inputs support 1.8-V and 3.3-V CMOS logic levels. 1.3 V
VIL Low-level input voltage 0.4 V
IIH High-level input current SDATA, SCLK, CS (1) VHIGH = 1.8 V 5 μA
IIL Low-level input current SDATA, SCLK, CS VLOW = 0 V 0 μA
DIGITAL CMOS OUTPUT – SDOUT
VOH High-level output voltage IOH = 100 µA AVDD – 0.05 V
VOL Low-level output voltage IOL = 100 µA 0.05 V
DIGITAL OUTPUTS – LVDS INTERFACE (OUT1P/M TO OUT8P/M, ADCLKP/M, LCLKP/M)
VODH High-level output differential voltage With external 100-Ω termination 275 370 465 mV
VODL Low-level output differential voltage With external 100-Ω termination –465 –370 –275 mV
VOCM Output common-mode voltage 1000 1200 1400 mV
(1) CS, SDATA, SCLK have internal 300-kΩ pulldown resistor.

7.9 Timing Requirements(1)

Typical values are at 25°C, AVDD = 3.3 V, LVDD = 1.8 V, sampling frequency = 100 MSPS, sine wave input clock = 1.5 Vpp clock amplitude, CLOAD = 5 pF(2), RLOAD = 100 Ω(3), unless otherwise noted. MIN and MAX values are across the full temperature range, TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, LVDD = 1.7 V to 1.9 V
MIN TYP MAX UNIT
tj Aperture jitter 220 fs rms
tA Aperture delay Time delay between rising edge of input clock and the actual sampling instant 3 ns
Wake-up time Time to valid data after coming out of STANDBY mode 10 μs
Time to valid data after coming out of global power down 60
ADC latency Latency of ADC alone, excludes the delay from input clock to output clock (tPDI), Figure 3 16 Clock cycles
2 WIRE, 8× SERIALIZATION (4)
tsu Data setup time Data valid (5) to zero-crossing of LCLKP 0.23 ns
th Data hold time Zero-crossing of LCLKP to data becoming invalid(5) 0.31 ns
tPDI Clock propagation delay Input clock rising edge crossover to output frame clock ADCLKP rising edge crossover, tPDI = (ts/4) + tdelay 6.8 8.8 10.8 ns
Variation of tPDI Between two devices at same temperature and LVDD supply ±0.6 ns
LVDS bit clock duty cycle Duty cycle of differential clock, (LCLKP-LCLKM) 50%
tRISE
tFALL		 Data rise time,
Data fall time		 Rise time measured from –100 mV to 100 mV,
Fall time measured from 100 mV to –100 mV
10 MSPS ≤ Sampling frequency ≤ 100 MSPS		 0.17 ns
tCLKRISE
tCLKFALL		 Output clock rise time,
Output clock fall time		 Rise time measured from –100 mV to 100 mV
Fall time measured from 100 mV to –100 mV
10 MSPS ≤ Sampling frequency ≤ 100 MSPS		 0.2 ns
(1) Timing parameters are ensured by design and characterization and not tested in production.
(2) CLOAD is the effective external single-ended load capacitance between each output pin and ground.
(3) RLOAD is the differential load resistance between the LVDS output pair.
(4) Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(5) Data valid refers to logic HIGH of 100 mV and logic LOW of –100 mV.

7.10 LVDS Timing at Lower Sampling Frequencies - 2 Wire, 8× Serialization

SAMPLING FREQUENCY, MSPS SETUP TIME HOLD TIME UNIT
MIN TYP MAX MIN TYP MAX
100 0.23 0.31 ns
80 0.47 0.47 ns
65 0.56 0.7 ns
50 0.66 1 ns
20 2.7 2.8 ns

7.11 LVDS Timing for 1 Wire 16× Serialization

SAMPLING FREQUENCY, MSPS SETUP TIME HOLD TIME UNIT
MIN TYP MAX MIN TYP MAX
65 0.15 0.31 ns
50 0.27 0.35 ns
40 0.45 0.55 ns
20 1.1 1.4 ns
Clock Propagation Delay
tPDI = (ts/8) + tdelay
10 MSPS < Sampling Frequency < 65 MSPS		 tdelay ns
MIN TYP MAX ns
6.8 8.8 10.8 ns

7.12 LVDS Timing for 2 Wire, 7× Serialization

SAMPLING FREQUENCY, MSPS SETUP TIME HOLD TIME UNIT
MIN TYP MAX MIN TYP MAX
100 0.29 0.39 ns
80 0.51 0.60 ns
65 0.58 0.82 ns
50 0.85 1.20 ns
20 3.2 3.3 ns
Clock Propagation Delay
tPDI = (ts/3.5) + tdelay
10 MSPS < Sampling Frequency < 100 MSPS		 tdelay ns
MIN TYP MAX ns
6.8 8.8 10.8 ns

7.13 LVDS Timing for 1 Wire, 14× Serialization

SAMPLING FREQUENCY, MSPS SETUP TIME HOLD TIME UNIT
MIN TYP MAX MIN TYP MAX
65 0.19 0.28 ns
50 0.37 0.42 ns
30 0.70 1.0 ns
20 1.3 1.5 ns
Clock Propagation Delay
tPDI = (ts/7) + tdelay
10 MSPS < Sampling Frequency < 65 MSPS		 tdelay ns
MIN TYP MAX ns
6.8 8.8 10.8 ns

7.14 Serial Interface Timing Requirements

Typical values at 25°C, MIN and MAX values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, LVDD = 1.8 V, unless otherwise noted.
MIN TYP MAX UNIT
fSCLK SCLK frequency (= 1/ tSCLK) > DC 20 MHz
tSLOADS CS to SCLK setup time 25 ns
tSLOADH SCLK to CS hold time 25 ns
tDS SDATA setup time 25 ns
tDH SDATA hold time 25 ns

7.15 Reset Switching Characteristics

Typical values at 25°C, MIN and MAX values across the full temperature range TMIN = –40°C to TMAX = 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 Power-on delay Delay from power up of AVDD and LVDD to RESET pulse active 1 ms
t2 Reset pulse duration Pulse duration of active RESET signal 50 ns
t3 Register write delay Delay from RESET disable to CS active 100 ns
ADS5263 reset_tim_las760.gif

NOTE:

A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset. For parallel interface operation, RESET has to be tied permanently HIGH.
Figure 1. Reset Timing Diagram
ADS5263 LVDS_tims_las760.gif Figure 2. LVDS Timing
ADS5263 Latency-diag_v2_SLAS760.gif Figure 3. Latency Diagram
ADS5263 LVDS_vo_lev_las760.gif Figure 4. LVDS Output Voltage Levels

7.16 Typical Characteristics

7.16.1 Typical Characteristic – 16-Bit ADC Mode

All plots are at 25°C, AVDD = 3.3 V, LVDD = 1.8 V, maximum-rated sampling frequency, sine-wave input clock = 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted).
ADS5263 G001_40_3_LAS760.gif Figure 5. FFT for 3-MHz Input Signal, fS = 40 MSPS
ADS5263 G003_80_3_LAS760.gif Figure 7. FFT for 3-MHz Input Signal, fS = 80 MSPS
ADS5263 G005_80_65_LAS760.gif Figure 9. FFT for 65-MHz Input Signal, fS = 80 MSPS
ADS5263 G007_100_15_LAS760.gif Figure 11. FFT for 15-MHz Input Signal, fS = 100 MSPS
ADS5263 FFT_130M_IF.png Figure 13. FFT for 130-MHz Input Signal, fS = 100 MSPS
ADS5263 G010_SFDR_INPUT_Frq.png Figure 15. SFDR vs Input Frequency
ADS5263 G012_SFDR_100MSPS_gain.png Figure 17. SFDR Across Gain
ADS5263 G014_PERF_ACROSS_AIN_LAS760.png Figure 19. Performance Across Input Amplitude,
Single Tone
ADS5263 G015_perf_VCM.png Figure 21. Performance vs Input Common-Mode Voltage
ADS5263 G017_SNR_across_temperature_samplerate_80MSPS.png Figure 23. SNR Across Temperature vs AVDD Supply, Sample Rate = 80 MSPS
ADS5263 SFDR_across_Temperature_samplerate=100MSPS.png Figure 25. SFDR Across Temperature
Sample Rate = 100 MSPS
ADS5263 Performance_across_LVDDSupply_samplerate=100MSPS.png Figure 27. Performance Across LVDD Supply
Sample Rate = 100 MSPS
ADS5263 G020_clk_duty_cycle.png Figure 29. Performance Across Input Clock Duty Cycle,
Sample Rate = 100 MSPS
ADS5263 G022_fin3_fa3_far_100_LAS760.gif Figure 31. Far-Channel Crosstalk Spectrum
ADS5263 G024_DNL_3_100_Vishwaas16_x2380R18_LAS760.png Figure 33. Differential Non-Linearity
ADS5263 G002_40_15_LAS760.gif Figure 6. FFT for 15-MHz Input Signal, fS = 40 MSPS
ADS5263 G004_80_15_LAS760.gif Figure 8. FFT for 15-MHz Input Signal, fS = 80 MSPS
ADS5263 G006_100_3_LAS760.gif Figure 10. FFT for 3-MHz Input Signal, fS = 100 MSPS
ADS5263 G008_100_65_LAS760.gif Figure 12. FFT for 65-MHz Input Signal, fS = 100 MSPS
ADS5263 G009_IMD_FFT_8_10_LAS760.gif Figure 14. FFT for 2-Tone Input Signal
ADS5263 G011_SNR_INPUT_Frq.png Figure 16. SNR vs Input Frequency
ADS5263 G013_SNR_100MSPS.png Figure 18. SNR Across Gain
ADS5263 G041_Perf_across_AIN_High_IF.png Figure 20. SNR Across Input Amplitude
vs Input Frequency
ADS5263 G016_SFDR_across_temperature_samplerate_80MSPS.png Figure 22. SFDR Across Temperature vs AVDD Supply, Sample Rate = 80 MSPS
ADS5263 G018_Performance_across_LVDD_Supply_samplerate_80MSPS.png Figure 24. Performance Across LVDD Supply Voltage,
Sample Rate = 80 MSPS
ADS5263 SNR_across_Temperature_samplerate=100MSPS.png Figure 26. SNR Across Temperature
Sample Rate = 100 MSPS
ADS5263 G019_Differential Clock Amplitude_LAS760.png Figure 28. Performance Across Input Clock Amplitude, Sample Rate = 100 MSPS
ADS5263 G021_Crosstalk_3V_3A_Near_LAS760.gif Figure 30. Near-Channel Crosstalk Spectrum,
Sample Rate = 100 MSPS
ADS5263 G023_INL_3_100_Vishwaas16_x2380R18_LAS760.png Figure 32. Integral Non-Linearity
ADS5263 G025_Histogram_Of_output_code.png
Figure 34. Histogram of Output Code
with Analog Inputs Shorted

7.16.2 Typical Characteristic – 14-Bit ADC Mode

ADS5263 G026_3_100_14bit_LAS760.gif Figure 35. FFT for 3-MHz Input Signal, fS = 100 MSPS
ADS5263 G028_65_100_14bit_LAS760.gif Figure 37. FFT for 65-MHz Input Signal, fS = 100 MSPS
ADS5263 G027_15_100_14bit_LAS760.gif Figure 36. FFT for 15-MHz Input Signal, fS = 100 MSPS

7.16.3 Typical Characteristics – Common Plots

ADS5263 G030_Digital_power_16bit_LAS760.png Figure 38. 16-Bit Digital Power Across Sampling Frequencies
ADS5263 G037_SNR_Contour_16BitADC.png
Figure 40. SNR Contour Across Sampling and Input Frequencies, 16-Bit ADC
ADS5263 G039_SNR_Contour_14BitADC.png Figure 42. SNR Contour Across Sampling and Input Frequencies, 14-Bit ADC
ADS5263 G031_Digital power_14 bit_LAS760.png Figure 39. 14-Bit Digital Power Across Sampling Frequencies
ADS5263 G038_SFDR_Contour_16BitADC.png
Figure 41. SFDR Contour Across Sampling and Input Frequencies, 16-Bit ADC
ADS5263 G040_SFDR_Contour_14BitADC.png Figure 43. SFDR Contour Across Sampling and Input Frequencies, 14-Bit ADC

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale