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DATA SHEET
ADS54J66 Quad-channel, 14-bit, 500-MSPS ADC with Integrated DDC
1 Features
- Quad channel
- 14-Bit resolution
- Maximum clock rate: 500 MSPS
- Input bandwidth (3 dB): 900 MHz
- On-chip dither
- Analog Input buffer with high-impedance input
- Output options:
- Rx: decimate-by-2 and -4 options with
Low-Pass lFilter - 200-MHz Complex bandwidth or 100-MHz real bandwidth support
- DPD FB: 500 MSPS
- 1.9-VPP Differential full-scale input
- JESD204B interface:
- Subclass 1 support
- 1 Lane per ADC Up to 10 Gbps
- Dedicated SYNC pin for pair of channels
- Support for multi-chip synchronization
- 72-Pin VQFN package (10 mm × 10 mm)
- Key specifications:
- Power dissipation: 675 mW/ch
- Spectral performance (un-decimated)
- fIN = 190 MHz IF at –1 dBFS:
- SNR: 69.5 dBFS
- NSD: –153.5 dBFS/Hz
- SFDR: 86 dBc (HD2, HD3),
93 dBFS (Non HD2, HD3)
- fIN = 370 MHz IF at –3 dBFS:
- SNR: 68.5 dBFS
- NSD: –152.5 dBFS/Hz
- SFDR: 81 dBc (HD2, HD3),
86 dBFS (Non HD2, HD3)
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