• Quad Channel
• 14-Bit Resolution
• Maximum Sampling Rate: 1 GSPS
• Maximum Output Sample Rate: 500 MSPS
• Analog Input Buffer With High-Impedance Input
• Input 3-dB Bandwidth: 1 GHz
• Output Options:
  • Rx: Decimate-by-2 and -4 Options With
    Low-Pass Filter
  • 200-MHz Complex Bandwidth or 100-MHz Real Bandwidth Support
  • DPD FB: 2x Decimation With 14-Bit Burst Mode Output
• 1.1-V_PP Differential Full-Scale Input
• JESD204B Interface:
  • Subclass 1 Support
  • 1 Lane per ADC Up to 10 Gbps
  • Dedicated SYNC Pin for Pair of Channels
• Support for Multi-Chip Synchronization
• 72-Pin VQFN Package (10 mm × 10 mm)
• Power Dissipation: 625 mW/Ch
• Spectral Performance
  (Burst Mode, High Resolution):
  • f_IN = 190 MHz IF at –1 dBFS:
    • SNR: 69 dBFS
    • NSD: –153 dBFS/Hz
    • SFDR: 86 dBc (HD2, HD3),
      95 dBFS (Non HD2, HD3)
  • f_IN = 370 MHz IF at –3 dBFS:
    • SNR: 68.5 dBFS
    • NSD: –152.5 dBFS/Hz
    • SFDR: 80 dBc (HD2, HD3),
      86 dBFS (Non HD2, HD3)

• Multi-Carrier GSM Cellular Infrastructure
  Base Stations
• Multi-Carrier Multi-Mode Cellular Infrastructure Base Stations
• Telecommunications Receivers
• Telecom DPD Observation Receivers

The ADS58J64 is a low-power, wide-bandwidth, 14-bit, 1-GSPS, quad-channel, telecom receiver device. The ADS58J64 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS58J64 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to a 200-MHz receive bandwidth. The ADS58J64 also supports a 14-bit, 500-MSPS output in burst mode, making the device suitable for a digital pre-distortion (DPD) observation receiver.

The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.

Simplified Block Diagram