The ADS7054 device belongs to a family of pin-to-pin compatible, high-speed, low-power, single-channel successive-approximation register (SAR) type analog-to-digital converters (ADCs). The device family includes multiple resolutions, throughputs, and analog input variants (see Table 1 for a list of devices).
The ADS7054 is a 14-bit, 1-MSPS SAR ADC that supports fully-differential inputs in the range of ±AVDD, for AVDD in the range of 1.65 V to 3.6 V.
The internal offset calibration feature maintains excellent offset specifications over the entire AVDD and temperature operating range.
The device supports an SPI-compatible serial interface that is controlled by the CS and SCLK signals. The input signal is sampled with the CS falling edge and SCLK is used for both conversion and serial data output. The device supports a wide digital supply range (1.65 V to 3.6 V), enabling direct interfacing to a variety of host controllers. The ADS7054 complies with the JESD8-7A standard for a normal DVDD range (1.65 V to 1.95 V).
The ADS7054 is available in an 8-pin, small, X2QFN package and is specified over the extended industrial temperature range (–40°C to +125°C). The small form-factor and extremely-low power consumption make this device suitable for space-constrained and battery-powered applications that require high-speed, high-resolution data acquisition.
PART NAME | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS7054 | X2QFN (8) | 1.50 mm × 1.50 mm |
DATE | REVISION | NOTES |
---|---|---|
December 2017 | * | Initial release. |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | CS | Digital input | Chip-select signal, active low |
2 | SDO | Digital output | Serial data out |
3 | SCLK | Digital input | Serial clock |
4 | DVDD | Supply | Digital I/O supply voltage |
5 | GND | Supply | Ground for power supply, all analog and digital signals are referred to this pin |
6 | AVDD | Supply | Analog power-supply input, also provides the reference voltage to the ADC |
7 | AINP | Analog input | Analog signal input, positive |
8 | AINM | Analog input | Analog signal input, negative |
MIN | MAX | UNIT | |
---|---|---|---|
AVDD to GND | –0.3 | 3.9 | V |
DVDD to GND | –0.3 | 3.9 | V |
AINP to GND | –0.3 | AVDD + 0.3 | V |
AINM to GND | –0.3 | AVDD + 0.3 | V |
Input current to any pin except supply pins | –10 | 10 | mA |
Digital input voltage to GND | –0.3 | DVDD + 0.3 | V |
Storage temperature, Tstg | –60 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
AVDD | Analog supply voltage range | 1.65 | 3.3 | 3.6 | V |
DVDD | Digital supply voltage range | 1.65 | 1.8 | 3.6 | V |
TA | Operating free-air temperature | –40 | 25 | 125 | °C |
THERMAL METRIC(1) | ADS7054 | UNIT | |
---|---|---|---|
RUG (X2QFN) | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 177.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 51.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 76.7 | °C/W |
ψJT | Junction-to-top characterization parameter | 1 | °C/W |
ψJB | Junction-to-board characterization parameter | 76.7 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG INPUT | ||||||
Full-scale input voltage span(1) | –AVDD | AVDD | V | |||
Absolute input voltage range | AINP to GND | –0.1 | AVDD + 0.1 | V | ||
AINM to GND | –0.1 | AVDD + 0.1 | ||||
Common-mode voltage | (AINP + AINM) / 2 | (AVDD / 2) – 0.1 | (AVDD / 2) + 0.1 | V | ||
CS | Sampling capacitance | 16 | pF | |||
SYSTEM PERFORMANCE | ||||||
Resolution | 14 | Bits | ||||
NMC | No missing codes | 14 | Bits | |||
INL(8) | Integral nonlinearity | –3 | ±0.9 | 3 | LSB(2) | |
DNL | Differential nonlinearity | –0.99 | ±0.5 | 1 | LSB | |
EO(8) | Offset error | After calibration(7) | –6 | ±1 | 6 | LSB |
dVOS/dT | Offset error drift with temperature | 1.75 | ppm/°C | |||
EG(8) | Gain error | –0.1 | ±0.01 | 0.1 | %FS | |
Gain error drift with temperature | 0.5 | ppm/°C | ||||
SAMPLING DYNAMICS | ||||||
tCONV | Conversion time | 18 × tSCLK | ns | |||
tACQ | Acquisition time | 230 | ns | |||
fSAMPLE | Maximum throughput rate | 24-MHz SCLK, AVDD = 1.65 V to 3.6 V | 1 | MHz | ||
Aperture delay | 3 | ns | ||||
Aperture jitter, RMS | 12 | ps | ||||
DYNAMIC CHARACTERISTICS | ||||||
SNR | Signal-to-noise ratio(4) | AVDD = 3.3 V, fIN = 2 kHz | 76 | 79.6 | dB | |
AVDD = 2.5 V, fIN = 2 kHz | 78.5 | |||||
THD | Total harmonic distortion(4)(3) | fIN = 2 kHz | –92 | dB | ||
fIN = 100 kHz | –90.8 | |||||
fIN = 200 kHz | –90 | |||||
SINAD | Signal-to-noise and distortion(4) | fIN = 2 kHz | 76 | 79.4 | dB | |
fIN = 100 kHz | 78.7 | |||||
fIN = 200 kHz | 78.5 | |||||
SFDR | Spurious-free dynamic range(4) | fIN = 2 kHz | 92 | dB | ||
fIN = 100 kHz | 91.7 | |||||
fIN = 200 kHz | 90 | |||||
BW(fp) | Full-power bandwidth | At –3 dB | 200 | MHz | ||
DIGITAL INPUT/OUTPUT (CMOS Logic Family) | ||||||
VIH | High-level input voltage(5) | 0.65 DVDD | DVDD + 0.3 | V | ||
VIL | Low-level input voltage(5) | –0.3 | 0.35 DVDD | V | ||
VOH | High-level output voltage(5) | At Isource = 500 µA | 0.8 DVDD | DVDD | V | |
At Isource = 2 mA | DVDD – 0.45 | DVDD | ||||
VOL | Low-level output voltage(5) | At Isink = 500 µA | 0 | 0.2 DVDD | V | |
At Isink = 2 mA | 0 | 0.45 | ||||
POWER-SUPPLY REQUIREMENTS | ||||||
AVDD | Analog supply voltage | 1.65 | 3 | 3.6 | V | |
DVDD | Digital I/O supply voltage | 1.65 | 3 | 3.6 | V | |
IAVDD | Analog supply current | AVDD = 3.3 V, fSAMPLE = 1 MSPS | 450 | 560 | µA | |
AVDD = 3.3 V, fSAMPLE = 100 kSPS | 47 | 55 | ||||
AVDD = 3.3 V, fSAMPLE = 10 kSPS | 5 | |||||
AVDD = 1.8 V, fSAMPLE = 1 MSPS | 230 | |||||
Static current with CS and SCLK high | 0.02 | |||||
IDVDD | Digital supply current | DVDD = 1.8 V, CSDO = 20 pF, output code = 2AAAh(6) |
250 | µA | ||
DVDD = 1.8 V, static current with CS and SCLK high | 0.01 |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
tCLK | Time period of SCLK | 41.66 | ns | ||
tsu_CSCK | Setup time: CS falling edge to SCLK falling edge | 7 | ns | ||
tht_CKCS | Hold time: SCLK rising edge to CS rising edge | 8 | ns | ||
tph_CK | SCLK high time | 0.45 | 0.55 | tSCLK | |
tpl_CK | SCLK low time | 0.45 | 0.55 | tSCLK | |
tph_CS | CS high time | 15 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tCYCLE(1) | Cycle time | 1000 | ns | |||
tCONV | Conversion time | 18 × tSCLK | ns | |||
tden_CSDO | Delay time: CS falling edge to data enable | 6.5 | ns | |||
td_CKDO | Delay time: SCLK rising edge to (next) data valid on SDO | 10 | ns | |||
tht_CKDO | SCLK rising edge to current data invalid | 2.5 | ns | |||
tdz_CSDO | Delay time: CS rising edge to SDO going to tri-state | 5.5 | ns |
SNR = 80.6 dB, THD = –91.6 dB, ENOB = 13.0 bits |
SNR = 76.6dB, THD = –90.6 dB, fIN = 200 kHz |
VIN = 0 (differential) |
SNR = 78.5 dB, THD = –89.5 dB, fIN = 100 kHz |
CS = DVDD |
The device complies with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V. Figure 32 shows voltage levels for the digital input and output pins.
The ADS7054 device belongs to a family of pin-to-pin compatible, high-speed, low-power, single-channel successive-approximation register (SAR) type analog-to-digital converters (ADCs). The device family includes multiple resolutions, throughputs, and analog input variants (see Table 1 for a list of devices).
The ADS7054 is a 14-bit, 1-MSPS SAR ADC that supports fully-differential inputs in the range of ±AVDD, for AVDD in the range of 1.65 V to 3.6 V (see the Analog Input section for details on the analog input pins).
The internal offset calibration feature (see the OFFCAL State section) maintains excellent offset specifications over the entire AVDD and temperature operating range.
The device supports an SPI-compatible serial interface that is controlled by the CS and SCLK signals. The input signal is sampled with the CS falling edge and SCLK is used for both, conversion and serial data output (see the Device Functional Modes section, Timing Requirements table, and Switching Characteristics table).
The device supports a wide digital supply range (1.65 V to 3.6 V), enabling direct interfacing to a variety of host controllers. The ADS7054 complies with the JESD8-7A standard (see the Digital Voltage Levels section) for a normal DVDD range (1.65 V to 1.95 V).
The ADS7054 is available in an 8-pin, small, X2QFN package (see the Mechanical, Packaging, and Orderable Information section for more details) and is specified over the extended industrial temperature range (–40°C to +125°C).
The small form-factor and extremely-low power consumption make this device suitable for space-constrained and battery-powered applications that require high-speed, high-resolution data acquisition (see the Application Information section).
The devices listed in Table 1 are all part of the same pin-to-pin compatible, high-speed, low-power, single-channel SAR ADC family. This device family includes multiple different ADC resolutions, throughputs, and analog input types to allow for greater flexibility in the end system. Devices in the same package are pin-compatible to offer a scalable family of devices for varying levels of end-system performance. The ADCs with device numbers ending in -Q1 are also AEC-Q100 qualified for automotive applications.
DEVICE NUMBER | RESOLUTION (Bits) | THROUGHPUT (MSPS) | INPUT TYPE | PACKAGES(1) |
---|---|---|---|---|
ADS7040 | 8 | 1 | Single-ended | X2QFN (8): 1.5 mm × 1.5 mm VSSOP (8): 2.0 mm × 3.1 mm |
ADS7041 | 10 | 1 | Single-ended | X2QFN (8): 1.5 mm × 1.5 mm VSSOP (8): 2.0 mm × 3.1 mm |
ADS7042 | 12 | 1 | Single-ended | X2QFN (8): 1.5 mm × 1.5 mm VSSOP (8): 2.0 mm × 3.1 mm |
ADS7043 | 12 | 1 | Pseudo-differential | X2QFN (8): 1.5 mm × 1.5 mm VSSOP (8): 2.0 mm × 3.1 mm |
ADS7044 | 12 | 1 | Fully-differential | X2QFN (8): 1.5 mm × 1.5 mm VSSOP (8): 2.0 mm × 3.1 mm |
ADS7029-Q1 | 8 | 2 | Single-ended | VSSOP (8): 2.0 mm × 3.1 mm |
ADS7039-Q1 | 10 | 2 | Single-ended | VSSOP (8): 2.0 mm × 3.1 mm |
ADS7049-Q1 | 12 | 2 | Single-ended | VSSOP (8): 2.0 mm × 3.1 mm |
ADS7046 | 12 | 3 | Single-ended | X2QFN (8): 1.5 mm × 1.5 mm |
ADS7047 | 12 | 3 | Fully-differential | X2QFN (8): 1.5 mm × 1.5 mm |
ADS7052 | 14 | 1 | Single-ended | X2QFN (8): 1.5 mm × 1.5 mm |
ADS7054 | 14 | 1 | Fully-differential | X2QFN (8): 1.5 mm × 1.5 mm |
ADS7056 | 14 | 2.5 | Single-ended | X2QFN (8): 1.5 mm × 1.5 mm |
ADS7057 | 14 | 2.5 | Fully-differential | X2QFN (8): 1.5 mm × 1.5 mm |
The device supports a unipolar, fully-differential analog input signal. Figure 33 shows a small-signal equivalent circuit of the sample-and-hold circuit. The sampling switch is represented by a resistance (RS1 and RS2, typically 50 Ω) in series with an ideal switch (SW1 and SW2). The sampling capacitors, CS1 and CS2, are typically 16 pF.
During the acquisition process, both positive and negative inputs are individually sampled on CS1 and CS2, respectively. During the conversion process, the device converts for the voltage difference between the two sampled values: VAINP – VAINM.
Each analog input pin has electrostatic discharge (ESD) protection diodes to AVDD and GND. Keep the analog inputs within the specified range to avoid turning the diodes on.
The full-scale analog input range (FSR) is VFSR = –AVDD to AVDD and the common-mode input voltage is AVDD / 2 ± 0.1 V.
The device uses the analog supply voltage (AVDD) as the reference voltage for the analog to digital conversion. During the conversion process, the internal capacitors are switched to the AVDD pin as per the successive approximation algorithm. A voltage reference must be selected with low temperature drift, high output current drive and low output impedance. TI recommends a 3.3-µF (CAVDD), low equivalent series resistance (ESR) ceramic capacitor between the AVDD and GND pins. This decoupling capacitor provides the instantaneous charge required by the internal circuit during the conversion process and maintains a stable dc voltage on the AVDD pin.
See the Power Supply Recommendations and Layout Example sections for component recommendations and layout guidelines.
The device supports a unipolar fully-differential analog input signal. The output is in two's compliment format. Figure 35 and Table 2 show the ideal transfer characteristics for the device.
The least significant bit for the device is given by:
where
INPUT VOLTAGE (AINP – AINM) | CODE | DESCRIPTION | IDEAL OUTPUT CODE (Hex) |
---|---|---|---|
≤ –(VREF – 1 LSB) | NFSC | Negative full-scale code | 2000 |
–(VREF – 1 LSB) to –(VREF – 2 LSB) | NFSC + 1 | — | 2001 |
0 LSB to 1 LSB | MC | Mid code | 0000 |
1 LSB to 2 LSB | MC + 1 | — | 0001 |
≥ VREF – 1 LSB | PFSC | Positive full-scale code | 1FFF |
The device supports a simple, SPI-compatible interface to the external host. On power-up, the device is in the ACQ state. The CS signal defines one conversion and serial data transfer frame. A frame starts with a CS falling edge and ends with a CS rising edge. The SDO pin is tri-stated when CS is high. With CS low, the clock provided on the SCLK pin is used for conversion and data transfer. Output data are available on the SDO pin.
As shown in Figure 36, the device supports three functional states: acquisition (ACQ), conversion (CNV), and offset calibration (OFFCAL). The device status depends on the CS and SCLK signals provided by the host controller.
In the ACQ state, switches SW1 and SW2 connected to the analog input pins close and the device acquires the analog input signal on CS1 and CS2. The device enters ACQ state at power-up, at the end of every conversion, and after completing the offset calibration. A CS falling edge takes the device from the ACQ state to the CNV state.
The device consumes extremely low power from the AVDD and DVDD power supplies when in ACQ state.
In the CNV state, the device uses the external clock to convert the sampled analog input signal to an equivalent digital code as per the transfer function illustrated in Figure 35. The conversion process requires a minimum of 18 SCLK falling edges to be provided within the frame. After the end of conversion process, the device automatically moves from the CNV state to the ACQ state. For acquisition of the next sample, a minimum time of tACQ must be provided.
Figure 37 shows a detailed timing diagram for the serial interface. In the first serial transfer frame after power-up, the device provides the first data as all zeros. In any frame, the clocks provided on the SCLK pin are also used to transfer the output data for the previous conversion. A leading 0 is output on the SDO pin on the CS falling edge. The most significant bit (MSB) of the output data is launched on the SDO pin on the rising edge after the first SCLK falling edge. Subsequent output bits are launched on the subsequent rising edges provided on SCLK. When all 14 output bits are shifted out, the device outputs 0's on the subsequent SCLK rising edges. The device enters the ACQ state after 18 clocks and a minimum time of tACQ must be provided for acquiring the next sample. If the device is provided with less than 18 SCLK falling edges in the present serial transfer frame, the device provides an invalid conversion result in the next serial transfer frame.
In the offset calibration (OFFCAL) state, the sampling capacitors are disconnected from the analog input pins (AINP and AINM) and the device calibrates and corrects for any internal offset errors. The offset calibration is effective for all subsequent conversions until the device is powered off. An offset calibration cycle is recommended at power-up and whenever there is a significant change in the operating conditions for the device (such as in the AVDD voltage and operating temperature).
The host controller must provide a serial transfer frame as described in Figure 38 or in Figure 39 to enter the OFFCAL state.
On power-up, the host must provide 24 SCLKs in the first serial transfer to enter the OFFCAL state. The device provides 0's on SDO during offset calibration. For acquisition of the next sample, a minimum time of tACQ must be provided.
If the host controller starts the offset calibration process but then pulls the CS pin high before providing 24 SCLKs, then the offset calibration process is aborted and the device enters the ACQ state. Figure 38 and Table 3 provide the timing for offset calibration on power-up.
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
tcycle | Cycle time for offset calibration on power-up | 24 × tCLK + tACQ | ns | ||
tACQ | Acquisition time | 230 | ns | ||
fSCLK | Frequency of SCLK | 24 | MHz |
During normal operation, the host must provide 64 SCLKs in the serial transfer frame to enter the OFFCAL state. The device provides the conversion result for the previous sample during the first 18 SCLKs and 0's on SDO for the rest of the SCLKs in the serial transfer frame. For acquisition of the next sample, a minimum time of tACQ must be provided.
If the host controller provides more than 18 SCLKs but pulls the CS high before providing 64 SCLKs, then the offset calibration process is aborted and the device enters the ACQ state. Figure 39 and Table 4 provide the timing for offset calibration during normal operation.
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
tcycle | Cycle time for offset calibration on power-up | 64 × tCLK + tACQ | ns | ||
tACQ | Acquisition time | 230 | ns | ||
fSCLK | Frequency of SCLK | 24 | MHz |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The two primary supporting circuits required to maximize the performance of a high-precision, successive approximation register (SAR) analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This section details some general principles for designing the input driver circuit, reference driver circuit, and provides typical application circuits designed for the device.
The goal of the circuit shown in Figure 40 is to design a two-channel, simultaneous-sampling data acquisition (DAQ) circuit based on the ADS7054 with an SNR greater than 79 dB and a THD less than –85 dB for input frequencies from 2 kHz to 50 kHz at a throughput of 1 MSPS. This simultaneous-sampling scheme is typically used in motor sine and cosine (sin-cos) encoders, resolvers, fish finders, sonar, and I-Q demodulation.
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and charge kickback filter. Careful design of the front-end circuit is critical to meet the linearity and noise performance of a high-precision ADC.
Figure 41 shows the input circuit of a typical SAR ADC. During the acquisition phase, the SW switch closes and connects the sampling capacitor (CSH) to the input driver circuit. This action introduces a transient on the input pins of the SAR ADC. An ideal amplifier with 0 Ω of output impedance and infinite current drive can settle this transient in zero time. For a real amplifier with non-zero output impedance and finite drive strength, this switched capacitor load can create stability issues.
For ac signals, the filter bandwidth must be kept low to band-limit the noise fed into the ADC input, thereby increasing the signal-to-noise ratio (SNR) of the system. Besides filtering the noise from the front-end drive circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC. A filter capacitor, CFLT, is connected across the ADC inputs. This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this capacitor is at least 20 times the specified value of the ADC sampling capacitance. For this device, the input sampling capacitance is equal to 16 pF. Thus, the value of CFLT is greater than 320 pF. Select a COG- or NPO-type capacitor because these capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying voltages, frequency, and time.
Driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability and distortion of the design.
The input amplifier bandwidth is typically much higher than the cutoff frequency of the charge kickback filter. Thus, TI strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some amplifiers can require more bandwidth than others to drive similar filters. To learn more about the SAR ADC input driver design, see the TI Precision Labs training video series.
The THS4551 is selected for its high bandwidth (135 MHz), low total harmonic distortion of –90 dBc at 100 kHz, and ultra-low noise of (3.2 nV/√Hz). The THS4551 is powered up from the power supply (VDD = 5 V and VSS = GND).
The ADS70xx uses the analog supply voltage (AVDD) as the reference voltage for the analog-to-digital conversion. During the conversion process, the internal capacitors are switched to the level of the AVDD pin as per the successive approximation algorithm. A voltage reference must be selected with low temperature drift, high output current drive, and low output impedance. For this application, the REF1933 was selected as the voltage reference and analog power supply for the ADC. The REF1933 has excellent temperature drift performance (25 ppm/°C), good initial accuracy (0.1%), high output drive capability (25 mA), and low quiescent current (360 µA). The REF1933 also provides a bias voltage output of half the reference voltage (VREF / 2) that can be used as the common-mode input for the amplifier.
TI recommends a 3.3-μF (CAVDD), low equivalent series resistance (ESR) ceramic capacitor between the AVDD and GND pins. This decoupling capacitor provides the instantaneous charge required by the internal circuit during the conversion process and maintains a stable dc voltage on the AVDD pin.
Figure 42 and Figure 43 provide the measurement results for the circuit described in Figure 40.
Device 1 | SNR = 80.3 dB, THD = –93 dB, SINAD = 79.6 dB | ||
Device 2 | SNR = 79.8 dB, THD = –92 dB, SINAD = 79.3 dB |
Device 1 | SNR = 79.2 dB, THD = –94 dB, SINAD = 78.9 dB | ||
Device 2 | SNR = 78.9 dB, THD = –92 dB, SINAD = 78.6 dB |
Some applications have sensor or signal inputs that are single ended. In order to increase the dynamic range, linearity, and precision of the system, such single-ended signals are often required to be interfaced with a differential input ADC. The goal of the design shown in Figure 44 is to interface a single-ended input source with the ADS7054 using a single-ended to differential front-end amplifier to achieve an SNR greater than 79 dB and a THD less than –85 dB for input frequencies up to 10 kHz at a throughput of 1 MSPS.
To achieve a SNR greater than 79 dB, the operational amplifier must have high bandwidth in order to settle the input signal within the acquisition time of the ADC. The operational amplifier must have low noise to keep the total system noise below 20% of the input-referred noise of the ADC. For the application circuit shown in Figure 44, the THS4551 is selected for its high bandwidth (135 MHz), low total harmonic distortion of –90 dBc at 100 kHz, and ultra-low noise of (3.2 nV/√Hz). The THS4551 is powered up from the power supply (VDD = 5 V and VSS = GND).
The THS4551 can be used in a single-ended to differential configuration as shown in Figure 44 without any performance degradation. This configuration enables single-ended input signals to be interfaced with differential input SAR ADCs (such as the ADS7054) to achieve higher system-level precision.
For this application, the REF1933 was selected as the voltage reference and analog power supply for the ADC. The REF1933 has excellent temperature drift performance (25 ppm/°C), good initial accuracy (0.1%), high output drive capability (25 mA), and low quiescent current (360 µA). The REF1933 also provides a bias voltage output of half the reference voltage (VREF / 2) that can be used as the common-mode input for the amplifier.