The ADS8671 and ADS8675 belong to a family of integrated data acquisition system based on a successive approximation (SAR) analog-to-digital converter (ADC). The devices feature a high-speed, high-precision SAR ADC, integrated analog front-end (AFE) input driver circuit, overvoltage protection circuit up to ±20 V, and an on-chip 4.096-V reference with extremely low temperature drift.
The devices operate on a single 5-V analog supply, but support true bipolar input ranges of ±12.288 V, ±6.144 V, ±10.24 V, ±5.12 V, and ±2.56 V, as well as unipolar input ranges of 0 V to 12.288 V, 0 V to 10.24 V, 0 V to 6.144 V, and 0 V to 5.12 V. The gain and offset errors are accurately trimmed within the specified values for each input range to ensure high dc precision. The input range selection is done by software programming of the device internal registers. The devices offer a high resistive input impedance (≥ 1 MΩ) irrespective of the selected input range.
The multiSPI digital interface is backward-compatible to the traditional SPI protocol. Additionally, configurable features simplify interface to a wide range of host controllers.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS866x | TSSOP (16) | 5.00 mm × 4.40 mm |
Changes from Revision A (October 2018) to Revision B (March 2021)
Changes from Revision * (December 2016) to Revision A (October 2018)
NAME | NO. | TYPE(1) | DESCRIPTION |
---|---|---|---|
TSSOP | |||
AGND | 3 | P | Analog ground pin. Decouple with the AVDD pin. |
AIN_GND | 8 | AI | Analog input: negative. Decouple with the AIN_P pin. |
AIN_P | 7 | AI | Analog input: positive. Decouple with the AIN_GND pin. |
ALARM/SDO-1/GPO | 14 | DO | Multi-function output pin. Active high alarm. Data output 1 for serial communication. General-purpose output pin. |
AVDD | 2 | P | Analog supply pin. Decouple with the AGND pin. |
CONVST/CS | 11 | DI | Dual-functionality pin. Active high logic: conversion start input pin; a CONVST rising edge brings the device from acquisition phase to conversion phase. Active low logic: chip-select input pin; the device takes control of the data bus when CS is low; the SDO-x pins go to tri-state when CS is high. |
DGND | 1 | P | Digital ground pin. Decouple with the DVDD pin. |
DVDD | 16 | P | Digital supply pin. Decouple with the DGND pin. |
REFCAP | 6 | AO | ADC reference buffer decoupling capacitor pin. Decouple with the REFGND pin. |
REFGND | 5 | P | Reference ground pin; short to the analog ground plane. Decouple with the REFIO and REFCAP pins. |
REFIO | 4 | AIO | Internal reference output and external reference input pin. Decouple with REFGND. |
RST | 9 | DI | Active low logic input to reset the device. |
RVS | 15 | DO | Multi-function output pin for serial interface; see the Section 7.4.2.1 section. With CS held high, RVS reflects the status of the internal ADCST signal. With CS low, the status of RVS depends on the output protocol selection. |
SCLK | 12 | DI | Serial communication: clock input pin for the serial interface. All system-synchronous data transfer protocols are timed with respect to the SCLK signal. |
SDI | 10 | DI | Dual
function: data input pin for serial communication. Chain data input during serial communication in daisy-chain mode. |
SDO-0 | 13 | DO | Serial communication: data output 0 |