Documentation available to aid IEC 61508 functional safety system design
Systematic capability up to SIL 3
Hardware integrity up to SIL 2 targeted
Safety-related certification
IEC 61508 certification planned
ECC or parity on calculation-critical memories
ECC and parity on select internal bus interconnects
Built-In Self-Test (BIST) for CPU and on-chip RAM
Error Signaling Module (ESM) with external error pin
Run-time safety diagnostics, including:
Voltage, Temperature, and Clock Monitoring
Windowed Watchdog Timers
CRC Engine for memory integrity checks
MCU domain with dedicated memory, interfaces, and M4F core capable of being isolated from the larger SoC with Freedom From Interference (FFI) features:
Separate interconnect
Firewalls and timeout gaskets
Controlled reset isolation
Dedicated MCU PLL and MMR control
Separate I/O Voltage Supply Rail
SoC architecture:
Supports primary boot from UART, I2C, OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, SD, eMMC, USB 2.0, PCIe, and Ethernet interfaces
16-nm FinFET technology
Package options:
ALV: 17.2 mm × 17.2 mm, 0.8 mm pitch (441-pin) FCBGA [Lidded] Flip-Chip Ball Grid Array ALV package
ALX: 11.0 mm × 11.0 mm, 0.5 mm pitch (293-pin) FC/CSP [SiP] Flip-Chip/Chip Scale Package ALX package