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  • bq51222 Dual Mode 5-W (WPC v1.2 and PMA) Single Chip Wireless Power Receiver

    • SLUSCL5A July   2016  – August 2016

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • bq51222 Dual Mode 5-W (WPC v1.2 and PMA) Single Chip Wireless Power Receiver
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Dynamic Rectifier Control
      2. 8.3.2  Dynamic Power Scaling
      3. 8.3.3  VO_REG and VIREG Calculations
      4. 8.3.4  RILIM Calculations
      5. 8.3.5  Adapter Enable Functionality
      6. 8.3.6  Turning Off the Transmitter
        1. 8.3.6.1 WPC End Power Transfer (EPT)
        2. 8.3.6.2 PMA EOC
      7. 8.3.7  CM_ILIM
      8. 8.3.8  PD_DET and TMEM
      9. 8.3.9  TS, Both WPC and PMA
      10. 8.3.10 I2C Communication
      11. 8.3.11 Input Overvoltage
    4. 8.4 Device Functional Modes
    5. 8.5 Register Maps
      1. 8.5.1  Wireless Power Supply Current Register 1 (address = 0x01) [reset = 00000001]
      2. 8.5.2  Wireless Power Supply Current Register 2 (address = 0x02) [reset = 00000111 ]
      3. 8.5.3  I2C Mailbox Register (address = 0xE0) [reset = 10000000 ]
      4. 8.5.4  Wireless Power Supply FOD RAM Register (address = 0xE1) [reset =00000000 ]
      5. 8.5.5  Wireless Power User Header RAM Register (address = 0xE2) [reset = 00000000]
      6. 8.5.6  Wireless Power USER VRECT Status RAM Register (address = 0xE3) [reset = 00000000]
      7. 8.5.7  Wireless Power VOUT Status RAM Register (address = 0xE4) [reset = 00000000]
      8. 8.5.8  Wireless Power REC PWR Byte Status RAM Register (address = 0xE8) [reset = 00000000]
      9. 8.5.9  Wireless Power Mode Indicator Register (address = 0xEF) [reset = 00000000]
      10. 8.5.10 Wireless Power Prop Packet Payload RAM Byte 0 Register (address = 0xF1) [reset = 00000000]
      11. 8.5.11 Wireless Power Prop Packet Payload RAM Byte 1 Register (address = 0xF2) [reset = 00000000]
      12. 8.5.12 Wireless Power Prop Packet Payload RAM Byte 2 Register (address = 0xF3) [reset = 00000000]
      13. 8.5.13 Wireless Power Prop Packet Payload RAM Byte 3 Register (address = 0xF4) [reset = 00000000]
      14. 8.5.14 RXID Readback Register (address = 0xF5 - 0xFA) [reset = see note]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Dual Mode Design (WPC and PMA Compliant) Power Supply 5-V Output with 1-A Maximum Current
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Output Voltage Set Point
          2. 9.2.1.2.2  Output and Rectifier Capacitors
            1. 9.2.1.2.2.1 TMEM
          3. 9.2.1.2.3  Maximum Output Current Set Point
          4. 9.2.1.2.4  TERM Resistor
          5. 9.2.1.2.5  Setting LPRB1 and LPRB2 Resistors
          6. 9.2.1.2.6  I2C
          7. 9.2.1.2.7  Communication Current Limit
          8. 9.2.1.2.8  Receiver Coil
          9. 9.2.1.2.9  Series and Parallel Resonant Capacitors
          10. 9.2.1.2.10 Communication, Boot and Clamp Capacitors
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Embedded in System Board
      3. 9.2.3 bq51222 Implemented in Back Cover
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • YFP|42
    • MXBG339A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • sluscl5a_oa
  • sluscl5a_pm
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

bq51222 Dual Mode 5-W (WPC v1.2 and PMA) Single Chip Wireless Power Receiver

1 Features

  • Robust 5-W Solution with 50% Lower Losses for Improved Thermals
    • Inductorless Receiver for Lowest Height Profile Solution
    • Adjustable Output Voltage (4.5 to 8 V) for Coil and Thermal Optimization
    • Fully Synchronous Rectifier with 96% Efficiency
    • 97% Efficient Post Regulator
    • 79% System Efficiency at 5 W
  • WPC v1.2 and PMA Compliant Communication
  • Patented Transmitter Pad Detect Function Improves User Experience
  • I2C Communication with Host

2 Applications

  • Smart Phones, Tablets, and Headsets
  • Wi-Fi Hotspots
  • Power Banks
  • Other Handheld Devices

3 Description

The bq51222 device is a fully contained wireless power receiver capable of operating in both the Wireless Power Consortium (WPC) Qi and Power Matters Alliance (PMA) protocols which allows a wireless power system to work with both inductive charging standards. The bq51222 device provides a single device power conversion (rectification and regulation) as well as the digital control and communication for both standards. It also has autonomous detection of protocol and requires no additional active devices. The bq51222 device complies with the WPC v1.2 and PMA communication protocol. Together with the WPC or a PMA primary-side controller, the bq51222 device enables a complete wireless power transfer system for a wireless power supply solution. The receiver allows for synchronous rectification, regulation and control and communication to all exist in a market-leading form factor, efficiency, and solution size.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (MAX)
bq51222 DSBGA (42) 3.586 mm × 2.874 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

SPACER

Simplified Schematic

bq51222 fp_simple_schem_sluscl5.gif

Dual Mode Efficiency 5-V Out

bq51222 D008_SLUSBS9.gif

4 Revision History

Changes from * Revision (July 2016) to A Revision

  • Changed from Product Preview to Production DataGo

5 Device Comparison Table

DEVICE MODE MORE
bq51221 Dual (WPC v1.1, PMA) Adjustable output voltage, highest system efficiency, I2C
bq51222 Dual (WPC v1.2, PMA) Adjustable output voltage, highest system efficiency, I2C
bq51021 WPC v1.1 Adjustable output voltage, highest system efficiency, I2C
bq51020 WPC v1.1 Adjustable output voltage, highest system efficiency, standalone

6 Pin Configuration and Functions

YFP Package
42-Pin DSBGA
Top View
bq51222 po_SLUSBS9.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NUMBER
AC1 B1, B2, B3 I AC input power from receiver resonant tank
AC2 B4, B5, B6 I
AD E2 I Adapter sense pin
AD-EN E3 O Push-pull driver for PFET that can pass AD input to the OUT pin; used for adapter mux control
BOOT1 C1 O Bootstrap capacitors for driving the high-side FETs of the synchronous rectifier
BOOT2 C6 O
COMM1 F1 O Open-drain FETs used to communicate with primary by varying reflected impedance
COMM2 F6 O
CLAMP1 E1 O Open-drain FETs used to clamp the secondary voltage by providing low impedance across secondary
CLAMP2 E6 O
CM_ILIM G3 I Enables or disables communication current limit; can be pulled high or low to disable or enable communication current limit
FOD F2 I Input that is used for scaling the received power message
ILIM G2 I/O Output current or overcurrent level programming pin
LPRB 1 F5 O Open drain – active to help drive RECT voltage high at light load on a PMA TX
LPRB 2 G6
OUT D1, D2, D3, D4, D5, D6 O Output pin, used to deliver power to the load
PD_DET G6 O Open drain output that allows user to sense when receiver is on transmitter
PGND A1, A2, A3, A4, A5, A6 — Power and logic ground
RECT C2, C3, C4, C5 O Filter capacitor for the internal synchronous rectifier
SCL E4 I SCL and SDA are used for I2C communication
SDA F4 I
TERM, LPRBEN F3 I Sets termination current as a percentage of IILIM as TERM pin. When TERM resistor is populated, LPRB pins are enabled with appropriate function
TMEM G5 O TMEM allows capacitor to be connected to GND so energy from transmitter ping can be stored to retain memory of state
TS/CTRL G4 I Temperature sense. Can be pulled high to send end power transfer (EPT) or end of charge (EOC) to TX
VIREG E5 I Rectifier voltage feedback
VO_REG G1 I Sets the regulation voltage for output
WPG F5 O Open-drain output that allows user to sense when power is transferred to load

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)(1) (2)
MIN MAX UNIT
Input voltage AC1, AC2 –0.8 20 V
RECT, COMM1, COMM2, OUT, LPRB1, LPRB2, CLAMP1, CLAMP2, WPG, PD_DET –0.3 20
AD, AD-EN –0.3 30
BOOT1, BOOT2 –0.3 20
SCL, SDA, TERM, CM_ILIM, FOD, TS/CTRL, ILIM, TMEM, VIREG, VO_REG, LPRBEN –0.3 7
Input current AC1, AC2 (RMS) 2.5 A
Output current OUT 1.5 A
Output sink current LPRB1, LPRB2 15 mA
Output sink current COMM1, COMM2 1 A
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) All voltages are with respect to the PGND pin, unless otherwise noted.
(2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD)(1) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(2), 100 pF, 1.5 kΩ ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(3) ±500
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VRECT RECT voltage range 4 10 V
IOUT Output current 1 A
IAD-EN Sink current 1 mA
ICOMM COMMx sink current 500 mA
TJ Junction temperature 0 125 ºC

7.4 Thermal Information

THERMAL METRIC(1) bq51222 UNIT
YFP (DSBGA)
42 PINS
RθJA Junction-to-ambient thermal resistance(2) 49.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance(3) 0.2 °C/W
RθJB Junction-to-board thermal resistance(4) 6.1 °C/W
ψJT Junction-to-top characterization parameter(5) 1.4 °C/W
ψJB Junction-to-board characterization parameter(6) 6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance(7) N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer

7.5 Electrical Characteristics

ILOAD = IOUT, over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VUVLO Undervoltage lockout VRECT: 0 to 3 V 2.8 2.9 V
VHYS-UVLO Hysteresis on UVLO VRECT: 3 to 2 V 393 mV
VRECT-OVP Input overvoltage threshold VRECT: 5 to 16 V 14.6 15.1 15.6 V
VHYS-OVP Hysteresis on OVP VRECT: 16 to 5 V 1.5 V
VRECT(REG) Voltage at RECT pin set by communication with primary VOUT + 0.12 VOUT + 2 V
VRECT(TRACK) VRECT regulation above VOUT VILIM = 1.2 V 140 mV
ILOAD-HYS ILOAD hysteresis for dynamic VRECT thresholds as a % of IILIM ILOAD falling 4%
VRECT-DPM Rectifier under voltage protection, restricts IOUT at VRECT-DPM 3 3.1 3.2 V
VRECT-REV Rectifier reverse voltage protection with a supply at the output VRECT-REV = VOUT – VRECT, VOUT = 10 V 8.8 9.2 V
ILPRB1-dis Current at which LPRB1 is disabled IOUT 0 to 200 mA 125 mA
ILPRB2-dis Current at which LPRB2 is disabled IOUT 0 to 400 mA 322 mA
QUIESCENT CURRENT
IOUT(standby) Quiescent current at the output when wireless power is disabled VOUT ≤ 5 V, 0°C ≤ TJ ≤ 85°C 20 35 µA
ILIM SHORT CIRCUIT
RILIM-SHORT Highest value of RILIM resistor considered a fault (short). Monitored for IOUT > 100 mA RILIM: 200 to 50 Ω. IOUT latches off, cycle power to reset 215 230 Ω
tDGL-Short Deglitch time transition from ILIM short to IOUT disable 1 ms
ILIM_SC ILIM-SHORT,OK enables the ILIM short comparator when IOUT is greater than this value ILOAD: 0 to 200 mA 110 125 140 mA
ILIM-SHORT,OK HYSTERESIS Hysteresis for ILIM-SHORT,OK comparator ILOAD: 200 to 0 mA 20 mA
IOUT-CL Maximum output current limit Maximum ILOAD that can be delivered for 1 ms when ILIM is shorted 3.7 A
OUTPUT
VO_REG Feedback voltage set point ILOAD = 1000 mA 0.495 0.5013 0.5075 V
ILOAD = 1 mA 0.4951 0.5014 0.5076
KILIM Current programming factor for hardware short circuit protection RILIM = KILIM / IILIM, where IILIM is the hardware current limit
IOUT = 850 mA		 842 AΩ
IOUT_RANGE Current limit programming range 1500 mA
ICOMM Output current limit during communication IOUT ≥ 400 mA IOUT – 50 mA
100 mA ≤ IOUT < 400 mA IOUT + 50
IOUT < 100 mA None
tHOLD-OFF Hold off time for the communication current limit during startup 1 s
TS/CTRL
VTS-Bias TS bias voltage (internal) ITS-Bias < 100 µA and communication is active (periodically driven, see tTS/CTRL-Meas) 1.8 V
VCTRL-HI CTRL pin threshold for a high VTS/CTRL: 50 to 150 mV 90 105 120 mV
TTS/CTRL-Meas Time period of TS/CTRL measurements, when TS is being driven TS bias voltage is only driven when power packets are sent 1700 ms
VTS-HOT Voltage at TS pin when device shuts down 0.38 V
THERMAL PROTECTION
TJ(OFF) Thermal shutdown temperature 155 °C
TJ(OFF-HYS) Thermal shutdown hysteresis 20 °C
OUTPUT LOGIC LEVELS ON WPG
VOL Open drain WPG pin ISINK = 5 mA 550 mV
IOFF,STAT WPG leakage current when disabled VWPG = 20 V 1 µA
COMM PIN
RDS-ON(COMM) COMM1 and COMM2 VRECT = 2.6 V 1 Ω
ƒCOMM Signaling frequency on COMMx pin for WPC 2.00 Kb/s
IOFF,COMM COMMx pin leakage current VCOMM1 = 20 V, VCOMM2 = 20 V 1 µA
CLAMP PIN
RDS-ON(CLAMP) CLAMP1 and CLAMP2 0.5 Ω
ADAPTER ENABLE
VAD-EN VAD rising threshold voltage VAD 0 V to 5 V 3.5 3.6 3.8 V
VAD-EN-HYS VAD-EN hysteresis VAD 5 V to 0 V 450 mV
IAD Input leakage current VRECT = 0 V, VAD = 5 V 50 μA
RAD_EN-OUT Pullup resistance from AD-EN to OUT when adapter mode is disabled and VOUT > VAD VAD = 0 V, VOUT = 5 V 230 350 Ω
VAD_EN-ON Voltage difference between VAD and VAD-EN when adapter mode is enabled VAD = 5 V, 0°C ≤ TJ ≤ 85°C 4 4.5 5 V
VAD = 9 V, 0°C ≤ TJ ≤ 85°C 3 6 7 V
SYNCHRONOUS RECTIFIER
ISYNC-EN IOUT at which the synchronous rectifier enters half synchronous mode IOUT: 200 mA to 0 mA 100 mA
ISYNC-EN-HYST Hysteresis for IOUT,RECT-EN (full-synchronous mode enabled) IOUT 0 mA to 200 mA 40 mA
VHS-DIODE High-side diode drop when the rectifier is in half synchronous mode IAC-VRECT = 250 mA, and
TJ = 25°C		 0.7 V
I2C
VIL Input low threshold level SDA V(PULLUP) = 1.8 V, SDA 0.4 V
VIH Input high threshold level SDA V(PULLUP) = 1.8 V, SDA 1.4 V
VIL Input low threshold level SCL V(PULLUP) = 1.8 V, SCL 0.4 V
VIH Input high threshold level SCL V(PULLUP) = 1.8 V, SCL 1.4 V
I2C speed Typical 100 kHz

7.6 Typical Characteristics

Temperature = 25°C (unless otherwise noted)
bq51222 D001_SLUSBS9.gif
Figure 1. Output Voltage Feedback as a Function of Load
bq51222 D003_SLUSBS9.gif
Figure 3. KILIM as a Function of Load Current
bq51222 D005_SLUSBS9.gif
Register 0x01 (B0, B1, B2)
1-mA Load
Figure 5. Register 0x01 control of VO_REG
bq51222 D002_SLUSBS9.gif
Figure 2. Quiescent Current as a Function of Output Voltage
bq51222 D004_SLUSBS9.gif
Figure 4. VUVLO as a Function of Junction Temperature
bq51222 D006_SLUSBS9.gif
Register 0x01 (B0, B1, B2)
1-A Load
Figure 6. Register 0x01 control of VO_REG

 
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