The CC2620 device is a wireless MCU targeting ZigBee® RF4CE remote control applications, both controller and target node.
The device is a member of the CC26xx family of cost-effective, ultralow power, 2.4-GHz RF devices. Very low active RF and MCU current and low-power mode current consumption provide excellent battery lifetime and allow for operation on small coin cell batteries and in energy-harvesting applications.
The CC2620 device contains a 32-bit ARM Cortex-M3 processor that runs at 48 MHz as the main processor and a rich peripheral feature set that includes a unique ultralow power sensor controller. This sensor controller is ideal for interfacing external sensors and for collecting analog and digital data autonomously while the rest of the system is in sleep mode. Thus, the CC2620 device is ideal for ZigBee RF4CE remote controls with features like voice, motion, RF-IR hybrid remotes, and qwerty keyboards and STB/target nodes with capacitive touch.
The IEEE 802.15.4 MAC is embedded into ROM and runs partly on an ARM Cortex-M0 processor. This architecture improves overall system performance and power consumption and frees up flash memory for the application.
Software stack support for this device includes: ZigBee RF4CE stack (RemoTI) which is available free of charge from www.ti.com.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
CC2620F128RGZ | VQFN (48) | 7.00 mm × 7.00 mm |
CC2620F128RSM | VQFN (32) | 4.00 mm × 4.00 mm |
Figure 1-1 shows a block diagram for the CC2620.
Changes from January 20, 2016 to July 5, 2016
Changes from December 2, 2015 to January 19, 2016
Changes from February 22, 2015 to December 2, 2015
DEVICE | PHY SUPPORT | FLASH (KB) | RAM (KB) | GPIO | PACKAGE(1) |
---|---|---|---|---|---|
CC2650F128xxx | Multi-Protocol(2) | 128 | 20 | 31, 15, 10 | RGZ, RHB, RSM |
CC2640F128xxx | Bluetooth low energy (Normal) | 128 | 20 | 31, 15, 10 | RGZ, RHB, RSM |
CC2630F128xxx | IEEE 802.15.4 Zigbee(/6LoWPAN) | 128 | 20 | 31, 15, 10 | RGZ, RHB, RSM |
CC2620F128xxx | IEEE 802.15.4 (RF4CE) | 128 | 20 | 31, 10 | RGZ, RSM |
NOTE:
I/O pins marked in bold have high drive capabilities. I/O pins marked in italics have analog capabilities.NAME | NO. | TYPE | DESCRIPTION |
---|---|---|---|
DCDC_SW | 33 | Power | Output from internal DC-DC(1) |
DCOUPL | 23 | Power | 1.27-V regulated digital-supply decoupling capacitor(2) |
DIO_0 | 5 | Digital I/O | GPIO, Sensor Controller |
DIO_1 | 6 | Digital I/O | GPIO, Sensor Controller |
DIO_2 | 7 | Digital I/O | GPIO, Sensor Controller |
DIO_3 | 8 | Digital I/O | GPIO, Sensor Controller |
DIO_4 | 9 | Digital I/O | GPIO, Sensor Controller |
DIO_5 | 10 | Digital I/O | GPIO, Sensor Controller, high-drive capability |
DIO_6 | 11 | Digital I/O | GPIO, Sensor Controller, high-drive capability |
DIO_7 | 12 | Digital I/O | GPIO, Sensor Controller, high-drive capability |
DIO_8 | 14 | Digital I/O | GPIO |
DIO_9 | 15 | Digital I/O | GPIO |
DIO_10 | 16 | Digital I/O | GPIO |
DIO_11 | 17 | Digital I/O | GPIO |
DIO_12 | 18 | Digital I/O | GPIO |
DIO_13 | 19 | Digital I/O | GPIO |
DIO_14 | 20 | Digital I/O | GPIO |
DIO_15 | 21 | Digital I/O | GPIO |
DIO_16 | 26 | Digital I/O | GPIO, JTAG_TDO, high-drive capability |
DIO_17 | 27 | Digital I/O | GPIO, JTAG_TDI, high-drive capability |
DIO_18 | 28 | Digital I/O | GPIO |
DIO_19 | 29 | Digital I/O | GPIO |
DIO_20 | 30 | Digital I/O | GPIO |
DIO_21 | 31 | Digital I/O | GPIO |
DIO_22 | 32 | Digital I/O | GPIO |
DIO_23 | 36 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
DIO_24 | 37 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
DIO_25 | 38 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
DIO_26 | 39 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
DIO_27 | 40 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
DIO_28 | 41 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
DIO_29 | 42 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
DIO_30 | 43 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
JTAG_TMSC | 24 | Digital I/O | JTAG TMSC, high-drive capability |
JTAG_TCKC | 25 | Digital I/O | JTAG TCKC |
RESET_N | 35 | Digital input | Reset, active-low. No internal pullup. |
RF_P | 1 | RF I/O | Positive RF input signal to LNA during RX Positive RF output signal to PA during TX |
RF_N | 2 | RF I/O | Negative RF input signal to LNA during RX Negative RF output signal to PA during TX |
VDDR | 45 | Power | 1.7-V to 1.95-V supply, typically connect to output of internal DC-DC(2)(3) |
VDDR_RF | 48 | Power | 1.7-V to 1.95-V supply, typically connect to output of internal DC-DC(2)(4) |
VDDS | 44 | Power | 1.8-V to 3.8-V main chip supply(1) |
VDDS2 | 13 | Power | 1.8-V to 3.8-V DIO supply(1) |
VDDS3 | 22 | Power | 1.8-V to 3.8-V DIO supply(1) |
VDDS_DCDC | 34 | Power | 1.8-V to 3.8-V DC-DC supply |
X32K_Q1 | 3 | Analog I/O | 32-kHz crystal oscillator pin 1 |
X32K_Q2 | 4 | Analog I/O | 32-kHz crystal oscillator pin 2 |
X24M_N | 46 | Analog I/O | 24-MHz crystal oscillator pin 1 |
X24M_P | 47 | Analog I/O | 24-MHz crystal oscillator pin 2 |
EGP | Power | Ground – Exposed Ground Pad |
NOTE:
I/O pins marked in bold have high drive capabilities. I/O pins marked in italics have analog capabilities.NAME | NO. | TYPE | DESCRIPTION |
---|---|---|---|
DCDC_SW | 18 | Power | Output from internal DC-DC. (1). Tie to ground for external regulator mode (1.7-V to 1.95-V operation) |
DCOUPL | 12 | Power | 1.27-V regulated digital-supply decoupling capacitor(2) |
DIO_0 | 8 | Digital I/O | GPIO, Sensor Controller, high-drive capability |
DIO_1 | 9 | Digital I/O | GPIO, Sensor Controller, high-drive capability |
DIO_2 | 10 | Digital I/O | GPIO, Sensor Controller, high-drive capability |
DIO_3 | 15 | Digital I/O | GPIO, High drive capability, JTAG_TDO |
DIO_4 | 16 | Digital I/O | GPIO, High drive capability, JTAG_TDI |
DIO_5 | 22 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
DIO_6 | 23 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
DIO_7 | 24 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
DIO_8 | 25 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
DIO_9 | 26 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
JTAG_TMSC | 13 | Digital I/O | JTAG TMSC |
JTAG_TCKC | 14 | Digital I/O | JTAG TCKC |
RESET_N | 21 | Digital Input | Reset, active-low. No internal pullup. |
RF_N | 2 | RF I/O | Negative RF input signal to LNA during RX Negative RF output signal to PA during TX |
RF_P | 1 | RF I/O | Positive RF input signal to LNA during RX Positive RF output signal to PA during TX |
RX_TX | 4 | RF I/O | Optional bias pin for the RF LNA |
VDDR | 28 | Power | 1.7-V to 1.95-V supply, typically connect to output of internal DC-DC. (2)(3) |
VDDR_RF | 32 | Power | 1.7-V to 1.95-V supply, typically connect to output of internal DC-DC(2)(4) |
VDDS | 27 | Power | 1.8-V to 3.8-V main chip supply(1) |
VDDS2 | 11 | Power | 1.8-V to 3.8-V GPIO supply(1) |
VDDS_DCDC | 19 | Power | 1.8-V to 3.8-V DC-DC supply. Tie to ground for external regulator mode (1.7-V to 1.95-V operation). |
VSS | 3, 7, 17, 20, 29 | Power | Ground |
X32K_Q1 | 5 | Analog I/O | 32-kHz crystal oscillator pin 1 |
X32K_Q2 | 6 | Analog I/O | 32-kHz crystal oscillator pin 2 |
X24M_N | 30 | Analog I/O | 24-MHz crystal oscillator pin 1 |
X24M_P | 31 | Analog I/O | 24-MHz crystal oscillator pin 2 |
EGP | Power | Ground – Exposed Ground Pad |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage (VDDS, VDDS2, and VDDS3) | VDDR supplied by internal DC-DC regulator or internal GLDO. VDDS_DCDC connected to VDDS on PCB. | –0.3 | 4.1 | V |
Supply voltage (VDDS(3) and VDDR) | External regulator mode (VDDS and VDDR pins connected on PCB) | –0.3 | 2.25 | V |
Voltage on any digital pin(4)(5) | –0.3 | VDDSx + 0.3, max 4.1 | V | |
Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X24M_N and X24M_P | –0.3 | VDDR + 0.3, max 2.25 | V | |
Voltage on ADC input (Vin) | Voltage scaling enabled | –0.3 | VDDS | V |
Voltage scaling disabled, internal reference | –0.3 | 1.49 | ||
Voltage scaling disabled, VDDS as reference | –0.3 | VDDS / 2.9 | ||
Input RF level | 5 | dBm | ||
Tstg | Storage temperature | –40 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
VESD | Electrostatic discharge (ESD) performance | Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1) | All pins | ±2500 | V |
Charged device model (CDM), per JESD22-C101(2) | RF pins | ±750 | |||
Non-RF pins | ±750 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Ambient temperature range | –40 | 85 | °C | |
Operating supply voltage (VDDS and VDDR), external regulator mode | For operation in 1.8-V systems (VDDS and VDDR pins connected on PCB, internal DC-DC cannot be used) |
1.7 | 1.95 | V |
Operating supply voltage VDDS | For operation in battery-powered and 3.3-V systems (internal DC-DC can be used to minimize power consumption) |
1.8 | 3.8 | V |
Operating supply voltages VDDS2 and VDDS3 | 0.7 × VDDS, min 1.8 | 3.8 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Icore | Core current consumption | Reset. RESET_N pin asserted or VDDS below Power-on-Reset threshold | 100 | nA | ||
Shutdown. No clocks running, no retention | 150 | |||||
Standby. With RTC, CPU, RAM and (partial) register retention. RCOSC_LF | 1 | µA | ||||
Standby. With RTC, CPU, RAM and (partial) register retention. XOSC_LF | 1.2 | |||||
Standby. With Cache, RTC, CPU, RAM and (partial) register retention. RCOSC_LF | 2.5 | |||||
Standby. With Cache, RTC, CPU, RAM and (partial) register retention. XOSC_LF | 2.7 | |||||
Idle. Supply Systems and RAM powered. | 550 | |||||
Active. Core running CoreMark | 1.45 mA + 31 µA/MHz |
|||||
Radio RX (1) | 5.9 | mA | ||||
Radio RX(2) | 6.1 | |||||
Radio TX, 0-dBm output power(1) | 6.1 | |||||
Radio TX, 5-dBm output power(2) | 9.1 | |||||
Peripheral Current Consumption (Adds to core current Icore for each peripheral unit activated)(3) | ||||||
Iperi | Peripheral power domain | Delta current with domain enabled | 20 | µA | ||
Serial power domain | Delta current with domain enabled | 13 | µA | |||
RF Core | Delta current with power domain enabled, clock enabled, RF core idle | 237 | µA | |||
µDMA | Delta current with clock enabled, module idle | 130 | µA | |||
Timers | Delta current with clock enabled, module idle | 113 | µA | |||
I2C | Delta current with clock enabled, module idle | 12 | µA | |||
I2S | Delta current with clock enabled, module idle | 36 | µA | |||
SSI | Delta current with clock enabled, module idle | 93 | µA | |||
UART | Delta current with clock enabled, module idle | 164 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
FLASH MEMORY | |||||
Supported flash erase cycles before failure | 100 | k Cycles | |||
Flash page/sector erase current | Average delta current | 12.6 | mA | ||
Flash page/sector size | 4 | KB | |||
Flash write current | Average delta current, 4 bytes at a time | 8.15 | mA | ||
Flash page/sector erase time(1) | 8 | ms | |||
Flash write time(1) | 4 bytes at a time | 8 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Output power, highest setting | Delivered to a single-ended 50-Ω load through a balun | 5 | dBm | ||
Output power, highest setting | Measured on CC2650EM-4XS, delivered to a single-ended 50-Ω load | 2 | dBm | ||
Output power, lowest setting | Delivered to a single-ended 50-Ω load through a balun | –21 | dBm | ||
Error vector magnitude | At maximum output power | 2% | |||
Spurious emission conducted measurement | f < 1 GHz, outside restricted bands | –43 | dBm | ||
f < 1 GHz, restricted bands ETSI | –65 | ||||
f < 1 GHz, restricted bands FCC | –76 | ||||
f > 1 GHz, including harmonics | –46 | ||||
Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan) |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
ESR Equivalent series resistance(2) | 6 pF < CL ≤ 9 pF | 20 | 60 | Ω | |
ESR Equivalent series resistance(2) | 5 pF < CL ≤ 6 pF | 80 | Ω | ||
LM Motional inductance(2) | Relates to load capacitance (CL in Farads) |
< 1.6 × 10–24 / CL2 | H | ||
CL Crystal load capacitance(2) | 5 | 9 | pF | ||
Crystal frequency(2)(3) | 24 | MHz | |||
Crystal frequency tolerance(2)(4) | –40 | 40 | ppm | ||
Start-up time(3)(5) | 150 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Crystal frequency(1) | 32.768 | kHz | ||||
ESR Equivalent series resistance(1) | 30 | 100 | kΩ | |||
CL Crystal load capacitance(1) | 6 | 12 | pF |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Frequency | 48 | MHz | |||
Uncalibrated frequency accuracy | ±1% | ||||
Calibrated frequency accuracy(1) | ±0.25% | ||||
Start-up time | 5 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Calibrated frequency(1) | 32.8 | kHz | |||
Temperature coefficient | 50 | ppm/°C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Input voltage range | 0 | VDDS | V | |||
Resolution | 12 | Bits | ||||
Sample rate | 200 | ksps | ||||
Offset | Internal 4.3-V equivalent reference(2) | 2 | LSB | |||
Gain error | Internal 4.3-V equivalent reference(2) | 2.4 | LSB | |||
DNL(4) | Differential nonlinearity | >–1 | LSB | |||
INL(5) | Integral nonlinearity | ±3 | LSB | |||
ENOB | Effective number of bits | Internal 4.3-V equivalent reference(2), 200 ksps, 9.6-kHz input tone |
9.8 | Bits | ||
VDDS as reference, 200 ksps, 9.6-kHz input tone | 10 | |||||
Internal 1.44-V reference, voltage scaling disabled, 32 samples average, 200 ksps, 300-Hz input tone |
11.1 | |||||
THD | Total harmonic distortion | Internal 4.3-V equivalent reference(2), 200 ksps, 9.6-kHz input tone |
–65 | dB | ||
VDDS as reference, 200 ksps, 9.6-kHz input tone | –69 | |||||
Internal 1.44-V reference, voltage scaling disabled, 32 samples average, 200 ksps, 300-Hz input tone |
–71 | |||||
SINAD, SNDR |
Signal-to-noise and Distortion ratio |
Internal 4.3-V equivalent reference(2), 200 ksps, 9.6-kHz input tone |
60 | dB | ||
VDDS as reference, 200 ksps, 9.6-kHz input tone | 63 | |||||
Internal 1.44-V reference, voltage scaling disabled, 32 samples average, 200 ksps, 300-Hz input tone |
69 | |||||
SFDR | Spurious-free dynamic range | Internal 4.3-V equivalent reference(2), 200 ksps, 9.6-kHz input tone |
67 | dB | ||
VDDS as reference, 200 ksps, 9.6-kHz input tone | 72 | |||||
Internal 1.44-V reference, voltage scaling disabled, 32 samples average, 200 ksps, 300-Hz input tone |
73 | |||||
Conversion time | Serial conversion, time-to-output, 24-MHz clock | 50 | clock-cycles | |||
Current consumption | Internal 4.3-V equivalent reference(2) | 0.66 | mA | |||
Current consumption | VDDS as reference | 0.75 | mA | |||
Reference voltage | Equivalent fixed internal reference (input voltage scaling enabled). For best accuracy, the ADC conversion should be initiated through the TIRTOS API in order to include the gain/offset compensation factors stored in FCFG1. | 4.3(2)(3) | V | |||
Reference voltage | Fixed internal reference (input voltage scaling disabled). For best accuracy, the ADC conversion should be initiated through the TIRTOS API in order to include the gain/offset compensation factors stored in FCFG1. This value is derived from the scaled value (4.3V) as follows: Vref=4.3V*1408/4095 | 1.48 | V | |||
Reference voltage | VDDS as reference (Also known as RELATIVE) (input voltage scaling enabled) | VDDS | V | |||
Reference voltage | VDDS as reference (Also known as RELATIVE) (input voltage scaling disabled) | VDDS / 2.82(3) | V | |||
Input Impedance | 200 ksps, voltage scaling enabled. Capacitive input, Input impedance depends on sampling frequency and sampling time | >1 | MΩ |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Resolution | 4 | °C | |||
Range | –40 | 85 | °C | ||
Accuracy | ±5 | °C | |||
Supply voltage coefficient(1) | 3.2 | °C/V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Resolution | 50 | mV | |||
Range | 1.8 | 3.8 | V | ||
Accuracy | 13 | mV |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Input voltage range | 0 | VDDS | V | ||
External reference voltage | 0 | VDDS | V | ||
Internal reference voltage | DCOUPL as reference | 1.27 | V | ||
Offset | 3 | mV | |||
Hysteresis | <2 | mV | |||
Decision time | Step from –10 mV to 10 mV | 0.72 | µs | ||
Current consumption when enabled(1) | 8.6 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Input voltage range | 0 | VDDS | V | ||
Clock frequency | 32 | kHz | |||
Internal reference voltage, VDDS / 2 | 1.49 – 1.51 | V | |||
Internal reference voltage, VDDS / 3 | 1.01 – 1.03 | V | |||
Internal reference voltage, VDDS / 4 | 0.78 – 0.79 | V | |||
Internal reference voltage, DCOUPL / 1 | 1.25 – 1.28 | V | |||
Internal reference voltage, DCOUPL / 2 | 0.63 – 0.65 | V | |||
Internal reference voltage, DCOUPL / 3 | 0.42 – 0.44 | V | |||
Internal reference voltage, DCOUPL / 4 | 0.33 – 0.34 | V | |||
Offset | <2 | mV | |||
Hysteresis | <5 | mV | |||
Decision time | Step from –50 mV to 50 mV | <1 | clock-cycle | ||
Current consumption when enabled | 362 | nA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Current source programmable output range | 0.25 – 20 | µA | |||
Resolution | 0.25 | µA | |||
Current consumption(1) | Including current source at maximum programmable output | 23 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
S1(1) tclk_per (SSIClk period) | Device operating as SLAVE | 12 | 65024 | system clocks | |
S2 (1) tclk_high (SSIClk high time) | Device operating as SLAVE | 0.5 | tclk_per | ||
S3(1) tclk_low (SSIClk low time) | Device operating as SLAVE | 0.5 | tclk_per | ||
S1 (TX only)(1) tclk_per (SSIClk period) | One-way communication to SLAVE - Device operating as MASTER | 4 | 65024 | system clocks | |
S1 (TX and RX)(1) tclk_per (SSIClk period) | Normal duplex operation - Device operating as MASTER | 8 | 65024 | system clocks | |
S2 (1) tclk_high (SSIClk high time) | Device operating as MASTER | 0.5 | tclk_per | ||
S3 (1) tclk_low(SSIClk low time) | Device operating as MASTER | 0.5 | tclk_per |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
TA = 25°C, VDDS = 1.8 V | |||||
GPIO VOH at 8-mA load | IOCURR = 2, high-drive GPIOs only | 1.32 | 1.54 | V | |
GPIO VOL at 8-mA load | IOCURR = 2, high-drive GPIOs only | 0.26 | 0.32 | V | |
GPIO VOH at 4-mA load | IOCURR = 1 | 1.32 | 1.58 | V | |
GPIO VOL at 4-mA load | IOCURR = 1 | 0.21 | 0.32 | V | |
GPIO pullup current | Input mode, pullup enabled, Vpad = 0 V | 71.7 | µA | ||
GPIO pulldown current | Input mode, pulldown enabled, Vpad = VDDS | 21.1 | µA | ||
GPIO high/low input transition, no hysteresis |
IH = 0, transition between reading 0 and reading 1 | 0.88 | V | ||
GPIO low-to-high input transition, with hysteresis |
IH = 1, transition voltage for input read as 0 → 1 | 1.07 | V | ||
GPIO high-to-low input transition, with hysteresis |
IH = 1, transition voltage for input read as 1 → 0 | 0.74 | V | ||
GPIO input hysteresis | IH = 1, difference between 0 → 1 and 1 → 0 points | 0.33 | V | ||
TA = 25°C, VDDS = 3.0 V | |||||
GPIO VOH at 8-mA load | IOCURR = 2, high-drive GPIOs only | 2.68 | V | ||
GPIO VOL at 8-mA load | IOCURR = 2, high-drive GPIOs only | 0.33 | V | ||
GPIO VOH at 4-mA load | IOCURR = 1 | 2.72 | V | ||
GPIO VOL at 4-mA load | IOCURR = 1 | 0.28 | V | ||
TA = 25°C, VDDS = 3.8 V | |||||
GPIO pullup current | Input mode, pullup enabled, Vpad = 0 V | 277 | µA | ||
GPIO pulldown current | Input mode, pulldown enabled, Vpad = VDDS | 113 | µA | ||
GPIO high/low input transition, no hysteresis |
IH = 0, transition between reading 0 and reading 1 | 1.67 | V | ||
GPIO low-to-high input transition, with hysteresis |
IH = 1, transition voltage for input read as 0 → 1 | 1.94 | V | ||
GPIO high-to-low input transition, with hysteresis |
IH = 1, transition voltage for input read as 1 → 0 | 1.54 | V | ||
GPIO input hysteresis | IH = 1, difference between 0 → 1 and 1 → 0 points | 0.4 | V | ||
TA = 25°C | |||||
VIH | Lowest GPIO input voltage reliably interpreted as a «High» | 0.8 | VDDS(1) | ||
VIL | Highest GPIO input voltage reliably interpreted as a «Low» | 0.2 | VDDS(1) |
NAME | DESCRIPTION | RSM (°C/W)(1)(2) | RGZ (°C/W)(1)(2) |
---|---|---|---|
RθJA | Junction-to-ambient thermal resistance | 36.9 | 29.6 |
RθJC(top) | Junction-to-case (top) thermal resistance | 30.3 | 15.7 |
RθJB | Junction-to-board thermal resistance | 7.6 | 6.2 |
PsiJT | Junction-to-top characterization parameter | 0.4 | 0.3 |
PsiJB | Junction-to-board characterization parameter | 7.4 | 6.2 |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.1 | 1.9 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
Rising supply-voltage slew rate | 0 | 100 | mV/µs | |||
Falling supply-voltage slew rate | 0 | 20 | mV/µs | |||
Falling supply-voltage slew rate, with low-power flash settings(1) | 3 | mV/µs | ||||
Positive temperature gradient in standby(3) | No limitation for negative temperature gradient, or outside standby mode | 5 | °C/s | |||
CONTROL INPUT AC CHARACTERISTICS(2) | ||||||
RESET_N low duration | 1 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
WAKEUP AND TIMING | ||||||
Idle → Active | 14 | µs | ||||
Standby → Active | 151 | µs | ||||
Shutdown → Active | 1015 | µs |