DATA SHEET
High Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting
1 Features
- Buffered inputs
- High current bus driver outputs
- Typical propagation delay
tPLH, tPHL = 8 ns
at VCC = 5 V, CL = 15 pF, TA = 25℃ - Fanout (over temperature
range)
- Standard outputs: 10 LSTTL Loads
- Bus driver outputs: 15 LSTTL Loads
- Wide operating temperature range: -55℃ to 125℃
- Balanced propagation delay and transition times
- Significant power reduction compared to LSTTL Logic ICs
- HC types
- 2 V to 6 V operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
- HCT types
- 4.5 V to 5.5 V operation
- Direct LSTTL input logic
compatibility,
VIL = 0.8 V (max), VIH = 2 V (min) - CMOS input compatibility, II ≤ 1µA at VOL,VOH
2 Description
The ’HC365, ’HCT365, and ’HC366 silicon gate CMOS three-state buffers are general purpose high-speed non-inverting and inverting buffers.
Device Information
| PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
|---|---|---|
| CD54HC365 | J (CERDIP, 16) | 19.56 x 6.92 mm |
| CD54HC366 | J (CERDIP, 16) | 19.56 x 6.92 mm |
| CD54HCT365 | J (CERDIP, 16) | 19.56 x 6.92 mm |
| CD74HC365 | N (PDIP, 16) | 19.30 x 6.35 mm |
| D (SOIC, 16) | 9.90 x 3.90 mm | |
| D (SOIC, 16) | 9.90 x 3.90 mm | |
| D (SOIC, 16) | 9.90 x 3.90 mm | |
| CD74HC366 | N (PDIP, 16) | 19.30 x 6.35 mm |
| D (SOIC, 16) | 9.90 x 3.90 mm | |
| D (SOIC, 16) | 9.90 x 3.90 mm | |
| CD74HCT365 | N (PDIP, 16) | 19.30 x 6.35 mm |
| D (SOIC, 16) | 9.90 x 3.90 mm | |
| D (SOIC, 16) | 9.90 x 3.90 mm | |
| D (SOIC, 16) | 9.90 x 3.90 mm |
(1) For all available packages, see
the orderable addendum at the end of the data sheet.
Logic Diagram for the HC/HCT365 and HC366 (Outputs for HC/HCT365 are
Complements of Those Shown, i.e., 1Y, 2Y, etc.)A. Inverter not included in HC/HCT 365.
3 Revision History
Changes from Revision C (October 2003) to Revision D (July 2022)
- Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standardsGo
4 Pin Configuration and Functions
Figure 4-1 CD54HC365, CD54HCT365, CD54HC366 (CERDIP) CD74HC365, CD74HCT365, CD74HC366
(PDIP, SOIC) Top View Table 4-1 Pin Functions
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | OE1 | I | Output Enable 1, Active Low |
| 2 | 1A | I | 1A Input |
| 3 | 1Y | O | 1Y Output |
| 4 | 2A | I | 2A Input |
| 5 | 2Y | O | 2Y Output |
| 6 | 3A | I | 3A Input |
| 7 | 3Y | O | 3Y Output |
| 8 | GND | — | Ground Pin |
| 9 | 4Y | O | 4Y Output |
| 10 | 4A | I | 4A Input |
| 11 | 5Y | O | 5Y Output |
| 12 | 5A | I | 5A Input |
| 13 | 6Y | O | 6Y Output |
| 14 | 6A | I | 6A Input |
| 15 | OE2 | I | Output Enable 2, Active Low |
| 16 | VCC | — | Power Pin |
(1) Signal Types: I = Input, O =
Output, I/O = Input or Output.
