SCHS122N November 1997 – April 2024 CD54HC4051 , CD54HC4052 , CD54HC4053 , CD54HCT4051 , CD74HC4051 , CD74HC4052 , CD74HC4053 , CD74HCT4051 , CD74HCT4052 , CD74HCT4053
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The CDx4HC405x and CDx4HCT405x device is a digitally controlled analog switch that uses silicon gate CMOS technology to achieve operating speeds similar to LSTTL with the low-power consumption of standard CMOS integrated circuits.
This analog multiplexer and demultiplexer controls analog voltages that may vary across the voltage supply range (for example, VCC to VEE). It is a bidirectional switch that allows any analog input to be used as an output and vice versa. The switch has low ON resistance and low OFF leakages. In addition, this device has an enable control that, when high, disables all switches to their OFF state.
PART NUMBER | TA | PACKAGE(1) | PACKAGE SIZE(2) |
---|---|---|---|
CD54HCx405x | -55°C to 125°C | J (CDIP, 16) | 19.56mm × 6.92mm |
CD74HCx405x | N (PDIP, 16) | 19.30mm × 6.35mm | |
D (SOIC, 16) | 9.9mm × 3.9mm | ||
NS (SOP, 16) | 10.3mm × 5.3mm | ||
PW (TSSOP, 16) | 5mm × 4.4mm |
PIN |
TYPE(1) |
DESCRIPTION |
|
---|---|---|---|
NAME |
NO. |
||
CH A4 IN/OUT |
1 |
I/O |
Channel 4 in/out |
CH A6 IN/OUT |
2 |
I/O | Channel 6 in/out |
COM OUT/IN |
3 |
I/O |
Common out/in |
CH A7 IN/OUT |
4 |
I/O | Channel 7 in/out |
CH A5 IN/OUT |
5 |
I/O | Channel 5 in/out |
!E |
6 |
I |
Enable Channels (Active Low) |
VEE |
7 |
— |
Negative power input |
GND |
8 |
— |
Ground |
S2 |
9 |
I |
Channel select 2 |
S1 |
10 |
I |
Channel select 1 |
S0 |
11 |
I |
Channel select 0 |
CH A3 IN/OUT |
12 |
I/O | Channel 3 in/out |
CH A0 IN/OUT |
13 |
I/O | Channel 0 in/out |
CH A1 IN/OUT |
14 |
I/O | Channel 1 in/out |
CH A2 IN/OUT |
15 |
I/O |
Channel 2 in/out |
VCC |
16 |
— |
Positive power input |
PIN |
TYPE(1) |
DESCRIPTION |
|
---|---|---|---|
NAME |
NO. |
||
CH B0 IN/OUT |
1 |
I/O |
Channel B0 in/out |
CH B2 IN/OUT |
2 |
I/O |
Channel B2 in/out |
COM B OUT/IN |
3 |
I/O |
B common out/in |
CH B3 IN/OUT |
4 |
I/O |
Channel B3 in/out |
CH B1 IN/OUT |
5 |
I/O |
Channel B1 in/out |
!E |
6 |
I |
Enable channels (Active Low) |
VEE |
7 |
— |
Negative power input |
GND |
8 |
— |
Ground |
S1 |
9 |
I |
Channel select 1 |
S0 |
10 |
I |
Channel select 0 |
CH A3 IN/OUT |
11 |
I/O |
Channel A3 in/out |
CH A0 IN/OUT |
12 |
I/O |
Channel A0 in/out |
COM A IN/OUT |
13 |
I/O |
A common out/in |
CH A1 IN/OUT |
14 |
I/O |
Channel A1 in/out |
CH A2 IN/OUT |
15 |
I/O |
Channel A2 in/out |
VCC |
16 |
— |
Positive power input |
PIN |
TYPE(1) |
DESCRIPTION |
|
---|---|---|---|
NAME |
NO. |
||
B1IN/OUT |
1 |
I/O |
B channel Y in/out |
B0 IN/OUT |
2 |
I/O |
B channel X in/out |
C1 IN/OUT |
3 |
I/O |
C channel Y in/out |
COM C OUT/IN |
4 |
I/O |
C common out/in |
C0 IN/OUT |
5 |
I/O |
C channel X in/out |
!E |
6 |
I |
Enable channels (Active Low) |
VEE |
7 |
— |
Negative power input |
GND |
8 |
— |
Ground |
S2 |
9 |
I |
Channel select 2 |
S1 |
10 |
I |
Channel select 1 |
S0 |
11 |
I |
Channel select 0 |
A0 IN/OUT |
12 |
I/O |
A channel X in/out |
A1 IN/OUT |
13 |
I/O |
A channel Y in/out |
COM A OUT/IN |
14 |
I/O |
A common out/in |
COM B OUT/IN |
15 |
I/O |
B common out/in |
VCC |
16 |
— |
Positive power input |