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  • CDx4HCT125 Quadruple Buffers with 3-State Outputs

    • SCHS415A June   2020  – August 2024 CD54HCT125 , CD74HCT125

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  • CDx4HCT125 Quadruple Buffers with 3-State Outputs
  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Operating Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS 3-State Outputs
      2. 7.3.2 TTL-Compatible CMOS Inputs
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • N|14
    • MPDI002C
  • D|14
    • MPDS177H
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • schs415a_oa
  • schs415a_pm
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Data Sheet

CDx4HCT125 Quadruple Buffers with 3-State Outputs

1 Features

  • LSTTL input logic compatible
    • VIL(max) = 0.8V, VIH(min) = 2V
  • CMOS input logic compatible
    • II ≤ 1µA at VOL, VOH
  • Buffered inputs
  • 4.5V to 5.5V operation
  • Wide operating temperature range: -55°C to +125°C
  • Supports fanout up to 10 LSTTL loads
  • Significant power reduction compared to LSTTL logic ICs

2 Applications

  • Enable digital signals

 
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