SNAS705D
January 2017 – February 2024
CDCE813-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements
5.7
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Control Terminal Configuration
7.3.2
Default Device Configuration
7.3.3
I2C Serial Interface
7.3.4
Data Protocol
7.4
Device Functional Modes
7.4.1
SDA and SCL Hardware Interface
7.5
Programming
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Spread-Spectrum Clock (SSC)
8.2.2.2
PLL Frequency Planning
8.2.2.3
Crystal Oscillator Start-Up
8.2.2.4
Frequency Adjustment With Crystal Oscillator Pulling
8.2.2.5
Unused Inputs and Outputs
8.2.2.6
Switching Between XO and VCXO Mode
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Register Maps
9.1
I2C Configuration Registers
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PW|14
MPDS360A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snas705d_oa
snas705d_pm
Data Sheet
CDCE813-Q1 Programmable 1-PLL Clock Synthesizer and Jitter Cleaner
With 2.5V and 3.3V Outputs