The CDCLVP1204 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1204 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1204 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. The CDCLVP1204 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP1204 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP1204 is characterized for operation from –40°C to +85°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
CDCLVP1204 | QFN (16) | 3.00 mm × 3.00 mm |
Changes from E Revision (September 2014) to F Revision
Changes from D Revision (June 2014) to E Revision
Changes from C Revision (August 2011) to D Revision
Changes from B Revision (May, 2010) to C Revision
Changes from A Revision (October, 2009) to B Revision
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NUMBER | ||
VCC | 5 | Power | 3.3-V supply for the device |
GND | 1 | Ground | Device ground |
INP0, INN0 | 6, 7 | Input | Differential input pair or single-ended input. Unused input pair can be left floating. |
INP1, INN1 | 3, 4 | Input | Redundant differential input pair or single-ended input. Unused input pair can be left floating. |
OUTP3, OUTN3 | 15, 16 | Output | Differential LVPECL output pair no. 3. Unused output pair can be left floating. |
OUTP2, OUTN2 | 13, 14 | Output | Differential LVPECL output pair no. 2. Unused output pair can be left floating. |
OUTP1, OUTN1 | 11, 12 | Output | Differential LVPECL output pair no. 1. Unused output pair can be left floating. |
OUTP0 OUTN0 | 9, 10 | Output | Differential LVPECL output pair no. 0. Unused output pair can be left floating. |
VAC_REF | 8 | — | Bias voltage output for capacitive-coupled inputs. Do not use VAC_REF at VCC < 3 V. If used, it is recommended to use a 0.1-μF capacitor to GND on this pin. The output current is limited to 2 mA. |
IN_SEL | 2 | — | Pulldown (see Terminal Characteristics) MUX select input for input choice (see Table 1) |
IN_SEL | ACTIVE CLOCK INPUT |
---|---|
0 | INP0, INN0 |
1 | INP1, INN1 |