SGLS390G July   2009  – November 2015 CDCM7005-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Automatic/Manual Reference Clock Switching
      2. 9.3.2 PLL Lock for Analog and Digital Detect
        1. 9.3.2.1 PLL Lock/Out-of-Lock Definition
        2. 9.3.2.2 Digital vs Analog Lock
      3. 9.3.3 Differential LVPECL Outputs and Single-Ended LVCMOS Outputs
      4. 9.3.4 Frequency Hold-Over Mode
      5. 9.3.5 Charge Pump Preset to VCC_CP / 2
      6. 9.3.6 Charge Pump Current Direction
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 SPI Control Interface
      2. 9.5.2 Functional Description of the Logic
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Clock Generation for Interpolating DACs With the CDCM7005-SP
        1. 10.1.1.1 AC-Coupled Interface to ADC/DAC
      2. 10.1.2 Phase Noise Performance
        1. 10.1.2.1 In-Band Noise Performance
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HFG|52
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • High Performance LVPECL and LVCMOS PLL Clock Synchronizer
  • Two Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support With Manual or Automatic Selection
  • Accepts LVCMOS Input Frequencies Up to
    200 MHz
  • VCXO_IN Clock is Synchronized to One of the Two Reference Clocks
  • VCXO_IN Frequencies Up to 2 GHz (LVPECL)
  • Outputs can be a Combination of LVPECL and LVCMOS (Up to Five Differential LVPECL Outputs or Up to 10 LVCMOS Outputs)
  • Output Frequency is Selectable by x1, /2, /3, /4, /6, /8, /16 on Each Output Individually
  • Efficient Jitter Cleaning from Low PLL Loop Bandwidth
  • Low Phase Noise PLL Core
  • Programmable Phase Offset (PRI_REF and SEC_REF to Outputs)
  • Wide Charge Pump Current Range From
    200 μA to 3 mA
  • Analog and Digital PLL Lock Indication
  • Provides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN)
  • Frequency Hold Over Mode Improves Fail-Safe Operation
  • Power-Up Control Forces LVPECL Outputs to Tri-State at VCC < 1.5 V
  • SPI Controllable Device Setting
  • 3.3-V Power Supply
  • High-Performance 52 Pin Ceramic Quad Flat Pack (HFG)
  • Rad-Tolerant : 50 kRad (Si) TID
  • QML-V Qualified, SMD 5962-07230
  • Military Temperature Range: –55°C to 125°C Tcase
  • Engineering Evaluation (/EM) Samples are Available (1)
(1)
(1)These units are intended for engineering evaluation only. They are processed to a non-compliant flow (for example, no burn-in, and so forth) and are tested to temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance on full MIL specified temperature range of –55°C to 125°C or operating life.

2 Applications

  • Low-Jitter Clock Distribution
  • SERDES Links
  • Analog Data Converters
  • Digital-to-Analog Converters

3 Description

The CDCM7005-SP is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O as VC(X)O_IN / PRI_REF = (N × P) / M or VC(X)O_IN / SEC_REF = (N × P) / M.

VC(X)O_IN clock operates up to 2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
CDCM7005-SP CFP (52) 13.97 mm × 13.97 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Schematic

CDCM7005-SP Key Graphic.gif

4 Revision History

Changes from F Revision (January 2014) to G Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Deleted two bullets from the Features List. Go

Changes from E Revision (August 2012) to F Revision

  • Added /EM bullet to FeaturesGo
  • Deleted Ordering Information tableGo

Changes from D Revision (December 2011) to E Revision

  • Changed PLL_LOCK pin description, replaced cycle-slip text.Go
  • Changed the Frequency Hold-Over Mode sectionGo
  • Changed text From: Cycle-Slip To: Frequency Offset in Figure 22Go
  • Changed table Word 3, Cycle Slip (Bit 6) To: Frequency OffsetGo
  • Changed Note 1 of table Word 3Go
  • Changed table Lock-Detect Window (Word 3) - Clip slip To: Frequency offset, and Note 2Go

Changes from B Revision (December 2009) to C Revision

  • Changed the VCC pin text - From: There is no internal connection between VCC and AVCC To: VCC and AVCC should always have same supply voltageGo
  • Added to the CTRL_LE - Unused or floating inputs must be tied to proper logic level. It is recommended to use a 20-kΩ or larger pullup resistor to VCCGo
  • Added to the CTRL_CLK pin - Unused or floating inputs must be tied to proper logic level. It is recommended to use a 20-kΩ or larger pullup resistor to VCCGo
  • Added to the CTRL_DATA pin - Unused or floating inputs must be tied to proper logic level. It is recommended to use a 20-kΩ or larger pullup resistor to VCCGo
  • Added to the PD pin text - It is recommended to ramp up the...Go
  • Added to the SPI CONTROL INTERFACE section - Unused or floating inputs must be tied to proper logic level. It is recommended to use a 20-kΩ or larger pullup resistor to VCCGo
  • Added to the SPI CONTROL INTERFACE section - It is recommended to program Word 0, Word 1, Word 2 and Word 3 right after power up and PD becomes HIGHGo
  • Changed bit 16 from RES to GTMEGo
  • Changed bit 28 from RES to PFDFCGo