• 650V GaN 功率 FET 半桥
• 170mΩ 低侧和 248mΩ 高侧 GaN FET
• 具有低传播延迟和可调节导通压摆率控制的集成栅极驱动器
• 具有高带宽和高精度的电流检测仿真
• 低侧/高侧栅极驱动互锁
• 高侧栅极驱动信号电平转换器
• 智能开关自举二极管功能
• 高侧启动：< 8us
• 低侧/高侧逐周期过流保护
• 通过 FLT 引脚报告实现过热保护
• AUX 空闲静态电流：240μA
• AUX 待机静态电流：50μA
• BST 空闲静态电流：60μA
• 最大电源和输入逻辑引脚电压：26V
• 具有双散热焊盘的 9mm x 7mm QFN 封装

• 有源钳位反激式电源转换器
• 交流/直流适配器和充电器
• 交流/直流 USB 墙壁插座电源
• 交流/直流辅助电源

LMG2610 是一款 650V GaN 功率 FET 半桥，适用于开关模式电源应用中 < 75W 的有源钳位反激式 (ACF) 转换器。LMG2610 通过在 9mm x 7mm QFN 封装中集成半桥功率 FET、栅极驱动器、自举二极管和高侧栅极驱动电平转换器，简化了设计、减少了元件数量并减小了布板空间。

非对称 GaN FET 电阻针对 ACF 工作条件进行了优化。可编程导通压摆率可提供 EMI 和振铃控制。与传统的电流检测电阻相比，低侧电流检测仿真可降低功耗，并允许将低侧散热焊盘连接到冷却 PCB 电源接地。

高侧栅极驱动信号电平转换器消除了外部解决方案中出现的噪声和突发模式功率耗散问题。智能开关 GaN 自举 FET 没有二极管正向压降，可避免高侧电源过充，并且反向恢复电荷为零。

LMG2610 具有低静态电流和快速启动时间，支持转换器轻负载效率要求和突发模式运行。保护特性包括 FET 导通互锁、欠压锁定 (UVLO)、逐周期电流限制和过热关断。

Figure 7-1 shows the circuit used to measure the GaN power FET switching parameters. The circuit is operated as a double-pulse tester. Consult external references for double-pulse tester details. The circuit is placed in the boost configuration to measure the low-side GaN switching parameters. The circuit is placed in the buck configuration to measure the high-side GaN switching parameters. The GaN FET not being measured in each configuration (high-side in the boost and low-side in the buck) acts as the double-pulse tester diode and circulates the inductor current in the off-state, third-quadrant conduction mode. Table 7-1 shows the details for each configuration.

Figure 7-2 shows the GaN power FET switching parameters.

The GaN power FET turn-on transition has three timing components: drain-current turn-on delay time, turn-on delay time, and turn-on rise time. Note that the turn-on rise time is the same as the V_DS 80% to 20% fall time. All three turn-on timing components are a function of the RDRVx pin setting.

The GaN power FET turn-off transition has two timing components: turn-off delay time, and turn-off fall time. Note that the turn-off fall time is the same as the V_DS 20% to 80% rise time. The turn-off timing components are independent of the RDRVx pin setting, but heavily dependent on the L_HB current.

The turn-on slew rate is measured over a smaller voltage delta (100 V) compared to the turn-on rise time voltage delta (240 V) to obtain a faster slew rate which is useful for EMI design. The RDRVx pin is used to program the slew rate.

The LMG2610 is a highly-integrated 650-V GaN power-FET half bridge intended for use in active-clamp flyback (ACF) converters. The LMG2610 combines the half-bridge power FETs, gate drivers, low-side current-sense emulation function, high-side gate-drive level shifter, and bootstrap diode function in a 9-mm by 7-mm QFN package.

The 650-V rated GaN power FETs support the large transformer turns ratios needed to minimize the secondary-side synchronous-rectifier voltage requirements in flyback converter applications. The GaN half-bridge low output-capacitive charge reduces both the time and energy needed for ACF zero-voltage switching (ZVS) and is the key characteristic needed to create small, efficient power converters.

The GaN half-bridge consists of a 170-mΩ low-side FET and a 248-mΩ high-side FET. The asymmetric GaN half-bridge FET sizes are a good utilization of total GaN FET size for ACF operating conditions.

The LMG2610 internal gate drivers regulate the drive voltage for optimum GaN power-FET on-resistance. Internal drivers also reduce total gate inductance and GaN FET common-source inductance for improved switching performance, including common-mode transient immunity (CMTI). The low-side / high-side GaN FET turn-on slew rates can be individually programmed to one of four discrete settings for design flexibility with respect to power loss, switching-induced ringing, and EMI.

Current-sense emulation places a scaled replica of the low-side drain current on the output of the CS pin. The CS pin is terminated with a resistor to AGND to create the current-sense input signal to the external power supply controller. This CS pin resistor replaces the traditional current-sense resistor, placed in series with the low-side GaN FET source, at significant power and space savings. Furthermore, with no current-sense resistor in series with the GaN source, the low-side GaN FET thermal pad can be connected directly to the PCB power ground. This thermal pad connection both improves system thermal performance and provides additional device routing flexibility since full device current can be conducted through the thermal pads.

The high-side gate-drive level-shifter reduces the capacitive coupling of the sensitive high-side gate drive path for lower noise susceptibility and better CMTI compared to external solutions where the signal path has a much larger PCB footprint. The level shifter also has minimal impact on device quiescent current and no impact on device start-up time compared to external solutions with worse quiescent current and start up performance.

The bootstrap diode function between AUX and BST is implemented with a smart-switched GaN bootstrap FET. The switched GaN bootstrap FET allows more complete charging of the BST-to-SW capacitor since the on-state GaN bootstrap FET does not have the forward voltage drop of a traditional bootstrap diode. The smart-switched GaN bootstrap FET also avoids the traditional bootstrap diode problem of BST-to-SW capacitor overcharging due to off-state third-quadrant current flow in the low-side half-bridge GaN power FET. Finally, the bootstrap function has more efficient switching due to low capacitance and no reverse-recovery charge compared to the traditional bootstrap diode.

The AUX input supply wide voltage range is compatible with the corresponding wide range supply rail created by power supply controllers. The BST input supply range is even wider on the low end to account for capacitive droop in between bootstrap recharge cycles. Low AUX / BST idle quiescent currents and fast BST start-up time support converter burst-mode operation critical for meeting government light-load efficiency mandates. Further AUX quiescent current reduction is obtained by placing the device in standby mode with the EN pin.

The INL, INH, and EN control pins have high input impedance, low input threshold voltage and maximum input voltage equal to the AUX voltage. This allows the pins to support both low voltage and high voltage input signals and be driven with low-power outputs.

The LMG2610 protection features are low-side / high-side under-voltage lockout (UVLO), low-side / high-side input gate-drive interlock, low-side / high-side cycle-by-cycle current limit, and over-temperature shut down. The UVLO features also help achieve well-behaved converter operation. The over-temperature shut down is reported on the open drain FLT output.

Due to the silicon FET’s long reign as the dominant power-switch technology, many designers are unaware that the nameplate drain-source voltage cannot be used as an equivalent point to compare devices across technologies. The nameplate drain-source voltage of a silicon FET is set by the avalanche breakdown voltage. The nameplate drain-source voltage of a GaN FET is set by the long term compliance to data sheet specifications.

Exceeding the nameplate drain-source voltage of a silicon FET can lead to immediate and permanent damage. Meanwhile, the breakdown voltage of a GaN FET is much higher than the nameplate drain-source voltage. For example, the breakdown drain-source voltage of the LMG2610 GaN power FET is more than 800 V which allows the LMG2610 to operate at conditions beyond an identically nameplate rated silicon FET.

The LMG2610 GaN power FET switching capability is explained with the assistance of Figure 8-1. The figure shows the drain-source voltage versus time for the LMG2610 GaN power FET for four distinct switch cycles in a switching application. No claim is made about the switching frequency or duty cycle. The first two cycles show normal operation and the second two cycles show operation during a rare input voltage surge. The LMG2610 GaN power FETs are intended to be turned on in either zero-voltage switching (ZVS) or discontinuous-conduction mode (DCM) switching conditions.

Each cycle starts before t₀ with the FET in the on state. At t₀ the GaN FET turns off and parasitic elements cause the drain-source voltage to ring at a high frequency. The high frequency ringing has damped out by t₁. Between t₁ and t₂ the FET drain-source voltage is set by the characteristic response of the switching application. The characteristic is shown as a flat line (plateau), but other responses are possible. At t₂ the GaN FET is turned on. For normal operation, the transient ring voltage is limited to 650 V and the plateau voltage is limited to 520 V. For rare surge events, the transient ring voltage is limited to 800 V and the plateau voltage is limited to 720 V.

The turn-on slew rate of both the low-side and high-side GaN power FETs are individually programmed to one of four discrete settings. The low-side slew rate is programmed by the resistance between the RDRVL and AGND pins. The high-side slew rate is programmed by the resistance between the RDRVH and SW pins. The low-side slew-rate setting is determined one time during AUX power up when the AUX voltage goes above the AUX Power-On Reset voltage. The high-side slew-rate setting is determined one time during BST-to-SW power up when the BST-to-SW voltage goes above the BST Power-On Reset voltage. The slew-rate setting determination time is not specified but is around 0.4 us.

Table 8-1 shows the recommended typical resistance programming value for the four slew rate settings and the typical turn-on slew rate at each setting. As noted in the table, an open-circuit connection is acceptable for programming slew-rate setting 0 and a short-circuit connection (RDRVL shorted to AGND for the low-side turn-on slew rate) (RDRVH shorted to SW for the high-side turn-on slew rate) is acceptable for programming slew-rate setting 3.

The current-sense emulation function creates a scaled replica of the low-side GaN power FET positive drain current at the output of the CS pin. The current-sense emulation gain, G_CSE, is 1 mA output from the CS pin, I_CS for every 1 A passing into the drain of the low-side GaN power FET, I_D.

The CS pin is terminated with a resistor to AGND, R_CS, to create the current-sense voltage input signal to the external power supply controller.

R_CS is determined by solving for the traditional current-sense design resistance, R_CS(trad), and multiplying by the inverse of G_CSE. The traditional current-sense design creates the current-sense voltage, V_CS(trad), by passing the low-side GaN power FET drain current, I_D, through R_CS(trad). The LMG2610 creates the current-sense voltage, V_CS, by passing the CS pin output current, I_CS, through R_CS. The current-sense voltage must be the same for both designs.

The CS pin is clamped internally to a typical 2.5 V. The clamp protects vulnerable power-supply controller current-sense input pins from over voltage if, for example, the current sense resistor on the CS pin were to become disconnected.

Figure 8-2 shows the current-sense emulation operation. In both cycles, the CS pin current emulates the low-side GaN power-FET drain current while the low-side FET is enabled. The first cycle shows normal operation where the controller turns off the low-side GaN power FET when the controller current-sense input threshold is tripped. The second cycle shows a fault situation where the LMG2610 Over-Current Protection turns off the low-side GaN power FET before the controller current-sense input threshold is tripped. In this second cycle, the LMG2610 avoids a hung controller INL pulse by generating a fast-ramping artificial current-sense emulation signal to trip the controller current-sense input threshold. The artificial signal persists until the INL pin goes to logic-low which indicates the controller is back in control of switch operation.

The internal bootstrap diode function is implemented with a smart-switched GaN bootstrap FET. The GaN bootstrap FET blocks current in both directions between AUX and BST when The GaN bootstrap FET is turned off.

The bootstrap diode function is active when the low-side GaN power FET is turned on and inactive when the low-side GaN power FET is turned off. The GaN bootstrap FET is held off in the bootstrap diode inactive phase. The GaN bootstrap FET is turned on a single time at the beginning of the bootstrap active phase and is controlled as an ideal diode with diode current flowing from AUX to BST to charge the BST-to-SW capacitor. If a small reverse current from BST to AUX is detected after the GaN bootstrap FET is turned on, the GaN bootstrap FET is turned off for the remainder of the bootstrap active phase.

The bootstrap diode function implements a current limit to protect the GaN bootstrap FET when the BST-to-SW capacitor is significantly discharged at the beginning of the bootstrap active phase. If there is no current limit situation during the GaN bootstrap FET turn on, or if the bootstrap function drops out of current limit as the BST-to-SW capacitor charges, the current limit function is disabled for the remainder of the GaN bootstrap FET turn-on time. The current limit function is disabled to save quiescent current.

The EN pin is used to toggle the device between the active and standby modes described in Device Functional Modes.

The INL pin is used to turn the low-side GaN power FET on and off.

The INH pin is used to turn the high-side GaN power FET on and off.

The input control pins have a typical 1-V input-voltage-threshold hysteresis for noise immunity. The pins also have a typical 400 kΩ pull-down resistance to protect against floating inputs. The 400 kΩ saturates for typical input voltages above 4 V to limit the maximum input pull-down current to a typical 10 uA.

The INL turn-on action is impacted by the following conditions 1) Standby Mode, 2) AUX UVLO, 3) INH in control of Interlock, 4) Low-Side Over-Current Protection, and 5) Over-Temperature Protection.

The INH turn-on action is impacted by the following conditions 1) Standby Mode, 2) AUX UVLO, 3) INL in control of Interlock, 4) High-Side Over-Current Protection, and 5) Over-Temperature Protection.

The Standby Mode, AUX UVLO, and Over-Temperature Protection are the universal INL / INH blocking conditions. These conditions hold both GaN half-bridge power FETs off independent of INL and INH. Figure 8-3 shows the Universal Blocking Condition Operation. Note that the high-side FET does not turn on at transistion #4. INH only turns on the high-side FET if there is no universal blocking condition when INH goes to logic high. This avoids an incomplete high-side FET turn-on period which can create undesired spike voltages in the converter.

The interlock function keeps the low-side and high-side GaN power FETs from being simultaneously turned on when the INL and INH pins are both logic-high. Either the INL or the INH pin gains control of the interlock if it is logic high when the other pin is logic low. Once the INL or INH pin gains control of the interlock, it retains control as long as it remains logic high. Only the INL or INH pin in control of the interlock passes a logic-high signal through the interlock.

The interlock is disabled if any of the universal INL / INH blocking conditions defined in Input Control Pins are asserted. When the interlock is disabled, the interlock outputs are held at logic low. If both INL and INH are logic-high when the interlock is enabled, the INL takes priority, gains control of the interlock, and passes the INL logic-high signal through the interlock.

The AUX pin is the input supply for the low-side internal circuits and is the power source to charge the BST-to-SW capacitor through the internal bootstrap diode function.

The AUX Power-On Reset disables all low-side functionality if the AUX voltage is below the AUX Power-On Reset voltage. The AUX Power-On Reset voltage is not specified but is around 5 V. The AUX Power-On Reset initates the one-time determination of the low-side slew-rate setting programmed on the RDRVL pin if the AUX voltage goes above the AUX Power-On Reset voltage. The AUX Power-On Reset enables the over-temperature protection function if the AUX voltage is above the AUX Power-On Reset voltage.

The AUX UVLO holds off both the low-side and high-side GaN power FETs if the AUX voltage is below the AUX UVLO voltage. The AUX UVLO voltage is set higher than the BST UVLO voltage so the high-side GaN power FET can be operated when the low-side GaN power FET is operating. The voltage separation between the AUX UVLO voltage and BST UVLO voltage accounts for operating conditions where the bootstrap charging of the BST-to-SW capacitor from the AUX supply is incomplete. The AUX UVLO voltage hysteresis prevents on-off chatter near the UVLO voltage trip point.