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UCC53x0 是单通道隔离式栅极驱动器系列,旨在驱动 MOSFET、IGBT、SiC MOSFET 和 GaN FET (UCC5350SBD)。UCC53x0S 提供分离输出,可分别控制上升和下降时间。UCC53x0M 将晶体管的栅极连接到内部钳位,以防止米勒电流造成假接通。UCC53x0E 的 UVLO2 以 GND2 为基准,以获取真实的 UVLO 读数。
UCC53x0 采用 4mm SOIC-8 (D) 或 8.5mm SOIC-8 (DWV) 封装,可分别支持高达 3kVRMS 和 5kVRMS 的隔离电压。凭借这些各种不同的选项,UCC53x0 系列成为电机驱动器和工业电源的理想之选。
与光耦合器相比,UCC53x0 系列的器件间偏移更低,传播延迟更小,工作温度更高,并且 CMTI 更高。
可订购器件型号(1)(2) | 最低拉电流和灌电流 | 说明 |
---|---|---|
UCC5310MC | 2.4A 和 1.1A | 米勒钳位 |
UCC5320SC | 2.4A 和 2.2A | 分离输出 |
UCC5320EC | 2.4A 和 2.2A | UVLO 以 IGBT 发射极为基准 |
UCC5350MC | 5A 和 5A | 米勒钳位 |
UCC5350SB | 5A 和 5A | 具有 8V UVLO 的分离输出 |
UCC5390SC | 10A 和 10A | 分离输出 |
UCC5390EC | 10A 和 10A | UVLO 以 IGBT 发射极为基准 |
DEVICE OPTION(1) | PACKAGE | MINIMUM SOURCE CURRENT | MINIMUM SINK CURRENT | PIN CONFIGURATION | UVLO | ISOLATION RATING |
---|---|---|---|---|---|---|
UCC5310MC | D | 2.4 A | 1.1 A | Miller clamp | 12 V | 3-kVRMS |
DWV | 5-kVRMS | |||||
UCC5320EC | D | 2.4 A | 2.2 A | UVLO with reference to GND2 | 12 V | 3-kVRMS |
UCC5320SC | D | 2.4 A | 2.2 A | Split output | 12 V | 3-kVRMS |
DWV | 5-kVRMS | |||||
UCC5350MC | D | 5 A | 5 A | Miller clamp | 12 V | 3-kVRMS |
DWV | 5-kVRMS | |||||
UCC5350SB | D | 5 A | 5 A | Split Output | 8 V | 3-kVRMS |
UCC5390EC | D | 10 A | 10 A | UVLO with reference to GND2 | 12 V | 3-kVRMS |
DWV | 5-kVRMS | |||||
UCC5390SC | D | 10 A | 10 A | Split output | 12 V | 3-kVRMS |
PIN | TYPE(1) | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | NO. | ||||
UCC53x0S | UCC53x0M | UCC53x0E | |||
CLAMP | — | 7 | — | I | Active Miller-clamp input found on the UCC53x0M used to prevent false turnon of the power switches. |
GND1 | 4 | 4 | 4 | G | Input ground. All signals on the input side are referenced to this ground. |
GND2 | — | — | 7 | G | Gate-drive common pin. Connect this pin to the IGBT emitter. UVLO referenced to GND2 in the UCC53x0E. |
IN+ | 2 | 2 | 2 | I | Noninverting gate-drive voltage-control input. The IN+ pin has a CMOS input threshold. This pin is pulled low internally if left open. Use Table 8-4 to understand the input and output logic of these devices. |
IN– | 3 | 3 | 3 | I | Inverting gate-drive voltage control input. The IN– pin has a CMOS input threshold. This pin is pulled high internally if left open. Use Table 8-4 to understand the input and output logic of these devices. |
OUT | — | 6 | 6 | O | Gate-drive output for UCC53x0E and UCC53x0M versions. |
OUTH | 6 | — | — | O | Gate-drive pull-up output found on the UCC53x0S. |
OUTL | 7 | — | — | O | Gate-drive pull-down output found on the UCC53x0S. |
VCC1 | 1 | 1 | 1 | P | Input supply voltage. Connect a locally decoupled capacitor to GND. Use a low-ESR or ESL capacitor located as close to the device as possible. |
VCC2 | 5 | 5 | 5 | P | Positive output supply rail. Connect a locally decoupled capacitor to VEE2. Use a low-ESR or ESL capacitor located as close to the device as possible. |
VEE2 | 8 | 8 | 8 | P | Negative output supply rail for E version, and GND for S and M versions. Connect a locally decoupled capacitor to GND2 for E version. Use a low-ESR or ESL capacitor located as close to the device as possible. |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Input bias pin supply voltage | VCC1 – GND1 | GND1 – 0.3 | 18 | V | |
Driver bias supply | VCC2 – VEE2 | –0.3 | 35 | V | |
VEE2 bipolar supply voltage for E version | VEE2 – GND2 | –17.5 | 0.3 | V | |
Output signal voltage | VOUTH – VEE2, VOUTL – VEE2, VOUT – VEE2, VCLAMP – VEE2 | VEE2 – 0.3 | VCC2 + 0.3 | V | |
Input signal voltage | VIN+ – GND1, VIN– – GND1 | GND1 – 5 | VCC1 + 0.3 | V | |
Junction temperature, TJ(2) | –40 | 150 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS–001(1) | ±4000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VCC1 | Supply voltage, input side | 3 | 15 | V | |
VCC2 | Positive supply voltage output side (VCC2 – VEE2), UCC53x0 | 13.2 | 33 | V | |
VCC2 | Positive supply voltage output side (VCC2 – VEE2), UCC5350SBD | 9.5 | 33 | V | |
VEE2 | Bipolar supply voltage for E version (VEE2 – GND2), UCC53x0 | –16 | 0 | V | |
VSUP2 | Total supply voltage output side (VCC2 – VEE2), UCC53x0 | 13.2 | 33 | V | |
TA | Ambient temperature | –40 | 125 | °C |
THERMAL METRIC(1) | UCC53x0 | UNIT | ||
---|---|---|---|---|
D (SOIC) | DWV (SOIC) | |||
8 PINS | 8 PINS | |||
RθJA | Junction–to-ambient thermal resistance | 109.5 | 119.8 | °C/W |
RθJC(top) | Junction–to-case (top) thermal resistance | 43.1 | 64.1 | °C/W |
RθJB | Junction–to-board thermal resistance | 51.2 | 65.4 | °C/W |
ΨJT | Junction–to-top characterization parameter | 18.3 | 37.6 | °C/W |
ΨJB | Junction–to-board characterization parameter | 50.7 | 63.7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
D Package | ||||||
PD | Maximum power dissipation on input and output | VCC1 = 15 V, VCC2 = 15 V, f = 2.1-MHz, 50% duty cycle, square wave, 2.2-nF load | 1.14 | W | ||
PD1 | Maximum input power dissipation | 0.05 | W | |||
PD2 | Maximum output power dissipation | 1.09 | W | |||
DWV Package | ||||||
PD | Maximum power dissipation on input and output | VCC1 = 15 V, VCC2 = 15 V, f = 1.9-MHz, 50% duty cycle, square wave, 2.2-nF load | 1.04 | W | ||
PD1 | Maximum input power dissipation | 0.05 | W | |||
PD2 | Maximum output power dissipation | 0.99 | W |
PARAMETER | TEST CONDITIONS | VALUE | UNIT | |
---|---|---|---|---|
D | ||||
CLR | External Clearance(1) | Shortest pin–to-pin distance through air | ≥ 4 | mm |
CPG | External Creepage(1) | Shortest pin–to-pin distance across the package surface | ≥ 4 | mm |
DTI | Distance through the insulation | Minimum internal gap (internal clearance) | > 21 | µm |
CTI | Comparative tracking index | DIN EN 60112 (VDE 0303–11); IEC 60112 | > 400 | V |
Material Group | According to IEC 60664–1 | II | ||
Overvoltage category per IEC 60664-1 | Rated mains voltage ≤ 150VRMS | I-IV | ||
Rated mains voltage ≤ 300VRMS | I-III | |||
DIN V VDE 0884–11: 2017–01(2) | ||||
VIORM | Maximum repetitive peak isolation voltage | AC voltage (bipolar) | 990(6) | VPK |
VIOWM | Maximum isolation working voltage | AC voltage (sine wave); time dependent dielectric breakdown (TDDB) test | 700(6) | VRMS |
DC Voltage | 990(6) | VDC | ||
VIOTM | Maximum transient isolation voltage | VTEST = VIOTM, t = 60 s
(qualification); VTEST = 1.2 × VIOTM, t = 1 s (100% production) |
4242 | VPK |
VIOSM | Maximum surge isolation voltage(3) | Test method per IEC 62368-1, 1.2/50-µs waveform, VTEST = 1.3 × VIOSM (qualification) | 4242 | VPK |
qpd | Apparent charge(4) | Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s Vpd(m) = 1.2 × VIORM, tm = 10 s |
≤ 5 | pC |
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM, tm = 10 s |
≤ 5 | |||
Method b1: At routine test (100% production) and preconditioning
(type test), Vini = 1.2 x VIOTM, tini = 1 s; Vpd(m) = 1.5 × VIORM, tm = 1 s |
≤ 5 | |||
CIO | Barrier capacitance, input to output(5) | VIO = 0.4 × sin (2πft), f = 1 MHz | 1.2 | pF |
RIO | Isolation resistance, input to output(5) | VIO = 500 V, TA = 25°C | > 1012 | Ω |
VIO = 500 V, 100°C ≤ TA ≤ 125°C | > 1011 | |||
VIO = 500 V at TS = 150°C | > 109 | |||
Pollution degree | 2 | |||
Climatic category | 40/125/21 | |||
UL 1577 | ||||
VISO | Withstand isolation voltage | VTEST = VISO, t = 60 s (qualification); VTEST = 1.2 × VISO, t = 1 s (100% production) | 3000 | VRMS |
PARAMETER | TEST CONDITIONS | VALUE | UNIT | ||
---|---|---|---|---|---|
DWV | |||||
CLR | External Clearance(1) | Shortest pin–to-pin distance through air | ≥ 8.5 | mm | |
CPG | External Creepage(1) | Shortest pin–to-pin distance across the package surface | ≥ 8.5 | mm | |
DTI | Distance through the insulation | Minimum internal gap (internal clearance) | > 21 | µm | |
CTI | Comparative tracking index | DIN EN 60112 (VDE 0303–11); IEC 60112 | > 600 | V | |
Material Group | According to IEC 60664–1 | I | |||
Overvoltage category per IEC 60664-1 | |||||
Rated mains voltage ≤ 600VRMS | I-III | ||||
Rated mains voltage ≤ 1000VRMS | I-II | ||||
DIN V VDE 0884–11: 2017–01(2) | |||||
VIORM | Maximum repetitive peak isolation voltage | AC voltage (bipolar) | 2121 | VPK | |
VIOWM | Maximum isolation working voltage | AC voltage (sine wave); time dependent dielectric breakdown (TDDB) test | 1500 | VRMS | |
DC Voltage | 2121 | VDC | |||
VIOTM | Maximum transient isolation voltage | VTEST = VIOTM, t = 60 s (qualification) ; VTEST = 1.2 × VIOTM, t = 1 s (100% production) | 7000 | VPK | |
VIOSM | Maximum surge isolation voltage(3) | Test method per IEC 62368-1, 1.2/50-µs waveform, VTEST = 1.6 × VIOSM (qualification) | 8000 | VPK | |
qpd | Apparent charge (4) | Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s Vpd(m) = 1.2 × VIORM, tm = 10 s | ≤ 5 | pC | |
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s | ≤ 5 | ||||
Method b1: At routine test (100% production) and preconditioning (type test), Vini = 1.2 x VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM, tm = 1 s | ≤ 5 | ||||
CIO | Barrier capacitance, input to output(5) | VIO = 0.4 × sin (2πft), f = 1 MHz | 1.2 | pF | |
RIO | Isolation resistance, input to output(5) | VIO = 500 V, TA = 25°C | > 1012 | Ω | |
VIO = 500 V, 100°C ≤ TA ≤ 125°C | > 1011 | ||||
VIO = 500 V at TS = 150°C | > 109 | ||||
Pollution degree | 2 | ||||
Climatic category | 40/125/21 | ||||
UL 1577 | |||||
VISO | Withstand isolation voltage | VTEST = VISO, t = 60 s (qualification); VTEST = 1.2 × VISO, t = 1 s (100% production) | 5000 | VRMS |
VDE | UL | CQC |
---|---|---|
Certified according to DIN V VDE V 0884–11:2017–01 and DIN EN 61010-1 (VDE 0411-1):2011-07 | Recognized under UL 1577 Component Recognition Program | Certified according to GB 4943.1–2011 |
Basic
Insulation Maximum Transient Isolation Overvoltage, 4242 VPK; Maximum Repetitive Peak Voltage, 990 VPK; Maximum Surge Isolation Voltage, 4242 VPK |
Single protection, 3000 VRMS | Basic Insulation, Altitude ≤ 5000m, Tropical Climate, 700 VRMS Maximum Working Voltage |
Certificate Number: 40047657 | File Number: E181974 | Certification number: CQC18001199354 |
VDE | UL | CQC | |
---|---|---|---|
Plan to certify according to DIN V VDE V 0884–11:2017–01 and DIN EN 61010-1 | Recognized under UL 1577 Component Recognition Program | Plan to certify according to GB 4943.1–2011 | |
Reinforced Insulation Maximum Transient Isolation Overvoltage, 7000 VPK; Maximum Repetitive Peak Isolation Voltage, 2121 VPK; Maximum Surge Isolation Voltage, 8000 VPK |
Single protection, 5000 VRMS | Reinforced
Insulation, Altitude ≤ 5000 m, Tropical Climate |
|
Certification number: 40047657 | File Number: E181974 | Certification planned |