The CSD87352Q5D NexFET™ power block is an optimized design for synchronous buck applications offering high-current, high-efficiency, and high-frequency capability in a small 5-mm × 6-mm outline. Optimized for 5-V gate drive applications, this product offers a flexible solution capable of offering a high-density power supply when paired with any 5-V gate drive from an external controller/driver.
DEVICE | MEDIA | QTY | PACKAGE | SHIP |
---|---|---|---|---|
CSD87352Q5D | 13-Inch Reel | 2500 | SON 5.00-mm × 6.00-mm Plastic Package |
Tape and Reel |
Typical Circuit![]() |
Typical Power Block Efficiency and Power Loss![]() |
Changes from C Revision (January 2012) to D Revision
Changes from B Revision (October 2011) to C Revision
Changes from A Revision (September 2011) to B Revision
Changes from * Revision (June 2011) to A Revision
PARAMETER | CONDITIONS | MIN | MAX | UNIT |
---|---|---|---|---|
Voltage | VIN to PGND | 30 | V | |
VSW to PGND | 30 | |||
VSW to PGND (10 ns) | 32 | |||
TG to TGR | –8 | 10 | ||
BG to PGND | –8 | 10 | ||
Pulsed current rating, IDM(2) | 60 | A | ||
Power dissipation, PD | 8.5 | W | ||
Avalanche energy, EAS | Sync FET, ID = 65 A, L = 0.1 mH | 211 | mJ | |
Control FET, ID = 37 A, L = 0.1 mH | 68 | |||
Operating junction, TJ | –55 | 150 | °C | |
Storage temperature, TSTG | –55 | 150 | °C |
PARAMETER | CONDITIONS | MIN | MAX | UNIT |
---|---|---|---|---|
Gate drive voltage, VGS | 4.5 | 8 | V | |
Input supply voltage, VIN | 27 | V | ||
Switching frequency, ƒSW | CBST = 0.1 μF (min) | 1500 | kHz | |
Operating current | 25 | A | ||
Operating temperature, TJ | 125 | °C |
PARAMETER | CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Power loss, PLOSS (1) | VIN = 12 V, VGS = 5 V, VOUT = 1.3 V, IOUT = 15 A, ƒSW = 500 kHz, LOUT = 0.3 µH, TJ = 25°C |
1.8 | W | ||
VIN quiescent current, IQVIN | TG to TGR = 0 V BG to PGND = 0 V |
10 | µA |
THERMAL METRIC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
RθJA | Junction-to-ambient thermal resistance (min Cu)(1)(2) | 150 | °C/W | ||
Junction-to-ambient thermal resistance (max Cu)(1)(2) | 82 | ||||
RθJC | Junction-to-case thermal resistance (top of package)(2) | 33 | °C/W | ||
Junction-to-case thermal resistance (PGND pin)(2) | 2.8 |
PARAMETER | TEST CONDITIONS | Q1 Control FET | Q2 Sync FET | UNIT | ||||||
---|---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | |||||
STATIC CHARACTERISTICS | ||||||||||
BVDSS | Drain-to-source voltage | VGS = 0 V, IDS = 250 μA | 30 | 30 | V | |||||
IDSS | Drain-to-source leakage current | VGS = 0 V, VDS = 24 V | 1 | 1 | μA | |||||
IGSS | Gate-to-source leakage current | VDS = 0 V, VGS = +10 / –8 V | 100 | 100 | nA | |||||
VGS(th) | Gate-to-source threshold voltage | VDS = VGS, IDS = 250 μA | 1 | 2.1 | 0.75 | 1.15 | V | |||
ZDS(on)(1) | Effective AC on-impedance | VIN = 12 V, VGS = 5 V, VOUT = 1.3 V, IOUT = 15 A, ƒSW = 500 kHz, LOUT = 0.3 µH, TJ = 25°C |
9 | 2.8 | mΩ | |||||
gfs | Transconductance | VDS = 15 V, IDS = 15 A | 51 | 87 | S | |||||
DYNAMIC CHARACTERISTICS | ||||||||||
CISS | Input capacitance | VGS = 0 V, VDS = 15 V, ƒ = 1 MHz |
740 | 890 | 1500 | 1800 | pF | |||
COSS | Output capacitance | 315 | 380 | 645 | 775 | pF | ||||
CRSS | Reverse transfer capacitance | 12 | 14 | 38 | 46 | pF | ||||
RG | Series gate resistance | 1.2 | 2.4 | 0.6 | 1.2 | Ω | ||||
Qg | Gate charge total (4.5 V) | VDS = 15 V, IDS = 15 A |
4.6 | 5.5 | 10.4 | 12.5 | nC | |||
Qgd | Gate charge gate-to-drain | 0.9 | 1.9 | nC | ||||||
Qgs | Gate charge gate-to-source | 1.5 | 2.2 | nC | ||||||
Qg(th) | Gate charge at Vth | 0.9 | 1.2 | nC | ||||||
QOSS | Output charge | VDS = 9.8 V, VGS = 0 V | 6.6 | 13 | nC | |||||
td(on) | Turnon delay time | VDS = 15 V, VGS = 4.5 V, IDS = 15 A, RG = 2 Ω |
5.4 | 6.1 | ns | |||||
tr | Rise time | 11 | 7 | ns | ||||||
td(off) | Turnoff delay time | 9.5 | 16 | ns | ||||||
tf | Fall time | 2 | 2.7 | ns | ||||||
DIODE CHARACTERISTICS | ||||||||||
VSD | Diode forward voltage | IDS = 15 A, VGS = 0 V | 0.8 | 0.8 | V | |||||
Qrr | Reverse recovery charge | Vdd = 9.8 V, IF = 15 A, di/dt = 300 A/μs |
11.3 | 16.3 | nC | |||||
trr | Reverse recovery time | 16 | 20 | ns |
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Max RθJA = 82°C/W when mounted on 1 in2 (6.45 cm2) of 2-oz (0.071-mm) thick Cu. |
![]() |
Max RθJA = 150°C/W when mounted on minimum pad area of 2-oz (0.071-mm) thick Cu. |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
Many of today’s high-performance computing systems require low power consumption in an effort to reduce system operating temperatures and improve overall system efficiency. This has created a major emphasis on improving the conversion efficiency of today’s synchronous buck topology. In particular, there has been an emphasis in improving the performance of the critical power semiconductor in the power stage of this application (see Figure 28). As such, optimization of the power semiconductors in these applications, needs to go beyond simply reducing RDS(ON).
The CSD87352Q5D is part of TI’s power block product family which is a highly optimized product for use in a synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest generation silicon which has been optimized for switching performance, as well as minimizing losses associated with QGD, QGS, and QRR. Furthermore, TI’s patented packaging technology has minimized losses by nearly eliminating parasitic elements between the control FET and sync FET connections (see Figure 29). A key challenge solved by TI’s patented packaging technology is the system level impact of Common Source Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI and modification of switching loss equations are outlined in Power Loss Calculation With Common Source Inductance Consideration for Synchronous Buck Converters (SLPA009).
The combination of TI’s latest generation silicon and optimized packaging technology has created a benchmarking solution that outperforms industry standard MOSFET chipsets of similar RDS(ON) and MOSFET chipsets with lower RDS(ON). Figure 30 and Figure 31 compare the efficiency and power loss performance of the CSD87352Q5D versus industry standard MOSFET chipsets commonly used in this type of application. This comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The performance of CSD87352Q5D clearly highlights the importance of considering the effective AC on-impedance (ZDS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET RDS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s power block technology.
The chart below compares the traditional DC measured RDS(ON) of CSD87352Q5D versus its ZDS(ON). This comparison takes into account the improved efficiency associated with TI’s patented packaging technology. As such, when comparing TI’s power block products to individually packaged discrete MOSFETs or dual MOSFETs in a standard package, the in-circuit switching performance of the solution must be considered. In this example, individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC measured RDS(ON) values that are equivalent to CSD87352Q5D’s ZDS(ON) value in order to have the same efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discrete MOSFETs or dual MOSFETs in a standard package.
PARAMETER | HS | LS | ||
---|---|---|---|---|
TYP | MAX | TYP | MAX | |
Effective AC on-impedance ZDS(ON) (VGS = 5 V) | 9 | — | 2.8 | — |
DC measured RDS(ON) (VGS = 4.5 V) | 9 | 10.8 | 4 | 4.8 |
The CSD87352Q5D NexFET™ power block is an optimized design for synchronous buck applications using 5-V gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems-centric environment. System-level performance curves such as power loss, Safe Operating Area (SOA), and normalized graphs allow engineers to predict the product performance in the actual application.
MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss performance curves. Figure 1 plots the power loss of the CSD87352Q5D as a function of load current. This curve is measured by configuring and running the CSD87352Q5D as it would be in the final application (see Figure 32). The measured power loss is the CSD87352Q5D loss and consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.
The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C under isothermal test conditions.
The SOA curves in the CSD87352Q5D data sheet provides guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 5 outline the temperature and airflow conditions required for a given load current. The area under the curve dictates the safe operating area. All the curves are based on measurements made on a PCB design with dimensions of 4 in (W) x 3.5 in (L) x 0.062 in (T) and 6 copper layers of 1-oz copper thickness.
The normalized curves in the CSD87352Q5D data sheet provides guidance on the power loss and SOA adjustments based on their application specific needs. These curves show how the power loss and SOA boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in power loss and the secondary Y-axis is the change is system temperature required in order to comply with the SOA curve. The change in power loss is a multiplier for the power loss curve and the change in temperature is subtracted from the SOA curve.
The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though the power loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following procedure will outline the steps the user should take to predict product performance for any set of system conditions.
Operating conditions:
In the design example above, the estimated power loss of the CSD87352Q5D would increase to 2.88 W. In addition, the maximum allowable board and/or ambient temperature would have to decrease by 3.5°C. Figure 33 graphically shows how the SOA curve would be adjusted accordingly.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient temperature of 3.5°C. In the event the adjustment value is a negative number, subtracting the negative number would yield an increase in allowable board/ambient temperature.
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief description on how to address each parameter is provided.
The power block has the ability to switch voltages at rates greater than 10 kV/µs. Special care must be then taken with the PCB layout design and placement of the input capacitors, Driver IC, and output inductor.
The power block has the ability to utilize the GND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that will wick down the via barrel:
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.