CSD87503Q3E 30-V N-Channel NexFET™ Power MOSFETs
- SLPS661 September 2017 CSD87503Q3E
  
  PRODUCTION DATA.

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DATA SHEET

CSD87503Q3E 30-V N-Channel NexFET™ Power MOSFETs

1 Features

Dual N-Ch Common Source MOSFETs
Optimized for 5-V Gate Drive
Low-Thermal Resistance
Low Q_g and Q_gd
Lead-Free Terminal Plating
RoHS Compliant
Halogen Free
SON 3.3-mm × 3.3-mm Plastic Package

2 Applications

USB Type-C/PD VBus Protection
Battery Protection
Load Switch

3 Description

The CSD87503Q3E is a 30-V, 13.5-mΩ, common source, dual N-channel device designed for USB Type-C/PD and battery protection. This SON 3.3 × 3.3 mm device has low drain-to-drain on-resistance that minimizes losses and offers low component count for space constrained applications.

Top View

Circuit Image

Product Summary

T_A = 25°C		VALUE		UNIT
V_DS	Drain-to-Source Voltage	30		V
Q_g	Gate Charge Total (4.5 V)	13.4		nC
Q_gd	Gate Charge Gate-to-Drain	5.8		nC
R_DD(on)	Drain-to-Drain On-Resistance	V_GS= 4.5 V	17.3	mΩ
R_DD(on)	Drain-to-Drain On-Resistance	V_GS = 10 V	13.5	mΩ
V_GS(th)	Threshold Voltage	1.7		V

Device Information⁽¹⁾

DEVICE	QTY	MEDIA	PACKAGE	SHIP
CSD87503Q3E	2500	13-Inch Reel	SON 3.30-mm × 3.30-mm Plastic Package	Tape and Reel
CSD87503Q3ET	250	7-Inch Reel	SON 3.30-mm × 3.30-mm Plastic Package	Tape and Reel

For all available packages, see the orderable addendum at the end of the data sheet.

Absolute Maximum Ratings

T_A = 25°C		VALUE	UNIT
V_DS	Drain-to-Source Voltage	30	V
V_GS	Gate-to-Source Voltage	±20	V
I_{D1, D2}	Continuous Drain-to-Drain Current (Package Limited)	10	A
I_DS	Continuous Drain-to-Source Current (Package Limited)	1.5	A
I_{D1, D2M}	Pulsed Drain-to-Drain Current,⁽¹⁾	89	A
P_D	Power Dissipation⁽²⁾	2.6	W
P_D	Power Dissipation, T_C = 25°C	15.6	W
T_J, T_stg	Operating Junction, Storage Temperature	–55 to 150	°C

Max R_θJC = 8°C/W, pulse duration ≤ 100 μs, duty cycle ≤ 1%.
Typical R_θJA = 50°C/W when mounted on a 1-in² (6.45-cm²), 2-oz (0.071-mm) thick Cu pad on a 0.06-in (1.52-mm) thick FR4 PCB.

R_DD(on) vs V_GS

4 Revision History

DATE	REVISION	NOTES
September 2017	*	Initial release.

5 Specifications

5.1 Electrical Characteristics

T_A = 25°C (unless otherwise stated)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
STATIC CHARACTERISTICS
BV_DSS	Drain-to-source voltage⁽¹⁾	V_GS = 0 V, I_D = 250 μA	30			V
I_DSS	Drain-to-source leakage current⁽¹⁾	V_GS = 0 V, V_DS = 24 V			1	μA
I_GSS	Gate-to-source leakage current⁽¹⁾	V_DS = 0 V, V_GS = 20 V			100	nA
V_GS(th)	Gate-to-source threshold voltage⁽¹⁾	V_DS = V_GS, I_D = 250 μA	1.3	1.7	2.1	V
R_DD(on)	Drain-to-drain on-resistance	V_GS = 4.5 V, I_D1D2 = 6 A		17.3	21.9	mΩ
R_DD(on)	Drain-to-drain on-resistance	V_GS = 10 V, I_D1D2 = 6 A		13.5	16.9	mΩ
g_fs	Transconductance	V_DS = 3 V, I_D1D2 = 6 A		24		S
DYNAMIC CHARACTERISTICS
C_ISS	Input capacitance	V_GS = 0 V, V_D1D2 = 15 V, ƒ = 1 MHz		782	1020	pF
C_OSS	Output capacitance			157	204	pF
C_RSS	Reverse transfer capacitance			149	194	pF
R_g	Series gate resistance⁽¹⁾			1.5	3.0	Ω
Q_g	Gate charge total (4.5 V)	V_D1D2 = 15 V, I_D1D2 = 6 A		13.4	17.4	nC
Q_g	Gate charge total (10 V)			32.9	42.8	nC
Q_gd	Gate charge gate-to-drain			5.8		nC
Q_gs	Gate charge gate-to-source			4.8		nC
Q_g(th)	Gate charge at V_th			1.0		nC
Q_OSS	Output charge	V_D1D2 = 15 V, V_GS = 0 V		4.3		nC
t_d(on)	Turnon delay time	V_D1D2 = 15 V, V_GS = 10 V, I_D1D2 = 6 A, R_G = 0 Ω		10		ns
t_r	Rise time			40		ns
t_d(off)	Turnoff delay time			25		ns
t_f	Fall time			8		ns
DIODE CHARACTERISTICS
V_SD	Diode forward voltage⁽¹⁾	I_D = 0.5 A, V_GS = 0 V		0.75	0.95	V
Q_rr	Reverse recovery charge⁽¹⁾	V_DS = 15 V, I_F = 6 A, di/dt = 300 A/μs		9.2		nC
t_rr	Reverse recovery time⁽¹⁾	V_DS = 15 V, I_F = 6 A, di/dt = 300 A/μs		14		ns

(1) Parameter measured on both MOSFETs individually. Table values are for a single FET.

5.2 Thermal Information

T_A = 25°C (unless otherwise stated)

THERMAL METRIC		MIN	TYP	MAX	UNIT
R_θJC	Junction-to-case thermal resistance⁽¹⁾			8	°C/W
R_θJA	Junction-to-ambient thermal resistance⁽¹⁾⁽²⁾			60	°C/W

(1) R_θJC is determined with the device mounted on a 1-in² (6.45-cm²), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in (3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 PCB. R_θJC is specified by design, whereas R_θJA is determined by the user’s board design.

(2) Device mounted on FR4 material with 1-in² (6.45-cm²), 2-oz (0.071-mm) thick Cu.

Max R_θJA = 60°C/W when mounted on 1 in² (6.45 cm²) of
2-oz (0.071-mm) thick Cu.

Max R_θJA = 185°C/W when mounted on a minimum pad area of
2-oz (0.071-mm) thick Cu.

5.3 Typical MOSFET Characteristics

T_A = 25°C (unless otherwise stated)

Figure 1. Transient Thermal Impedance


Note: Measurement taken with both gates tied together

Figure 2. Saturation Characteristics

I_D1D2 = 6 A

V_D1D2 = 15 V

Figure 4. Gate Charge

I_D = 250 µA

Figure 6. Threshold Voltage vs Temperature

	I_D1D2 = 6 A	V_D1D2 = 15 V
Note: Measurement taken with both gates tied together

Figure 8. Normalized On-State Resistance vs Temperature

	Single pulse, max R_θJC = 8°C/W

Figure 10. Maximum Safe Operating Area

Figure 12. Maximum Drain Current vs Temperature

	V_D1D2 = 5 V

Figure 3. Transfer Characteristics

Figure 5. Capacitance

Figure 7. On-State Resistance vs Gate-to-Source Voltage

Figure 9. Typical Diode Forward Voltage

Figure 11. Single Pulse Unclamped Inductive Switching

6 Device and Documentation Support

6.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

6.2 Community Resources

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6.3 Trademarks

E2E is a trademark of Texas Instruments.

6.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

6.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.