CSD95472Q5MC Synchronous Buck NexFET Smart Power Stage

1 Features

60-A Continuous Operating Current Capability
94.4% System Efficiency at 1.2 V / 30 A
Low Power Loss of 2.3 W at 30 A
High-Frequency Operation (up to 1.25 MHz)
Diode Emulation Mode With FCCM
Temperature-Compensated Bidirectional Current Sense
Analog Temperature Output (600 mV at 0°C)
Fault Monitoring
- High-Side Short, Overcurrent, and Overtemperature Protection
3.3-V and 5-V PWM Signal Compatible
Tri-State PWM Input
Integrated Bootstrap Diode
Optimized Deadtime for Shoot-Through Protection
High-Density SON 5 × 6 mm Footprint
Ultralow Inductance Package
System-Optimized PCB Footprint
DualCool™ Packaging
RoHS Compliant – Lead-Free Terminal Plating
Halogen Free

2 Applications

Multiphase Synchronous Buck Converters
- High-Frequency Applications
- High-Current, Low Duty Cycle Applications
POL DC-DC Converters
Memory and Graphic Cards

3 Description

The CSD95472Q5MC NexFET™ smart power stage is a highly optimized design for use in a high-power, high-density synchronous buck converter. This product integrates the driver IC and Power MOSFETs to complete the power stage switching function. This combination produces high-current, high-efficiency, and high-speed switching capability in a small 5 mm × 6 mm outline package. It also integrates the accurate current sensing and temperature sensing functionality to simplify system design and improve accuracy. In addition, the PCB footprint has been optimized to help reduce design time and simplify the completion of the overall system design.

Device Information⁽¹⁾

DEVICE	MEDIA	QTY	PACKAGE	SHIP
CSD95472Q5MC	13-Inch Reel	2500	SON 5 × 6 mm DualCool Package	Tape and Reel
CSD95472Q5MCT	7-Inch Reel	250	SON 5 × 6 mm DualCool Package	Tape and Reel

(1) For all available packages, see the orderable addendum at the end of the data sheet.

SPACER

Application Diagram

CSD95472Q5MC Front_Page_Application_SLPS565.gif

Typical Power Stage Efficiency and Power Loss

4 Revision History

DATE	REVISION	NOTES
February 2016	*	Initial release.

5 Pin Configuration and Functions

Top View

Pin Functions

PIN		DESCRIPTION
NUMBER	NAME	DESCRIPTION
1	IOUT	Output of current sensing amplifier. V(IOUT) – V(REFIN) is proportional to the phase current.
2	REFIN	External reference voltage input for current sensing amplifier.
3	ENABLE	Enables device operation. If ENABLE = logic HIGH, turns on device. If ENABLE = logic LOW, the device is turned off and both MOSFET gates are actively pulled low. An internal 100 kΩ pulldown resistor will pull the ENABLE pin LOW if left floating.
4	P_GND	Power ground, connected directly to pin 13.
5	V_DD	Supply voltage to gate driver and internal circuitry.
6	V_SW	Phase node connecting the HS MOSFET source and LS MOSFET drain – pin connection to the output inductor.
7	V_IN	Input voltage pin. Connect input capacitors close to this pin.
8	BOOT_R	Return path for HS gate driver, connected to V_SW internally.
9	BOOT	Bootstrap capacitor connection. Connect a minimum of 0.1 µF 16 V X7R ceramic capacitor from BOOT to BOOT_R pins. The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is integrated.
10	FCCM	This pin enables the diode emulation function. When this pin is held LOW, diode emulation mode is enabled for sync FET. When FCCM is HIGH, the device is operated in forced continuous conduction mode. An internal 5 µA current source will pull the FCCM pin to 3.3 V if left floating.
11	TAO/ FAULT	Temperature Analog Output. Reports a voltage proportional to the die temperature. An ORing diode is integrated in the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of all the ICs. Only the highest temperature will be reported. TAO will be pulled up to 3.3 V if thermal shutdown occurs. TAO should be bypassed to P_GND with a 1 nF 16 V X7R ceramic capacitor.
12	PWM	Pulse width modulated tri-state input from external controller. Logic LOW sets control FET gate low and sync FET gate high. Logic HIGH sets control FET gate high and sync FET gate low. Open or High Z sets both MOSFET gates low if greater than the tri-state shutdown hold-off time (t_3HT).
13	P_GND	Power ground.