SNAS395F December 2007 – October 2016 DAC121C081 , DAC121C085
PRODUCTION DATA.
The DAC121C081 is a 12-bit, single-channel, voltage-output digital-to-analog converter (DAC) that operates from a 2.7-V to 5.5-V supply. The output amplifier allows rail-to-rail output swing and has an 8.5-µs settling time. The DAC121C081 uses the supply voltage as the reference to provide the widest dynamic output range, and typically consumes 132 µA while operating at 5 V. It is available in 6-pin SOT and WSON packages, and provides three address options (pin selectable).
As an alternative, the DAC121C085 provides nine I2C addressing options and uses an external reference. It has the same performance and settling time as the DAC121C081, and is available in an 8-lead VSSOP.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DAC121C081 | WSON (6) | 2.20 mm × 2.50 mm |
SOT (6) | 1.60 mm × 2.90 mm | |
DAC121C085 | VSSOP (8) | 3.00 mm × 3.00 mm |
Changes from E Revision (January 2016) to F Revision
Changes from D Revision (March 2013) to E Revision
Changes from C Revision (March 2013) to D Revision
The DAC121C081 and DAC121C085 use a 2-wire, I2C-compatible serial interface that operates in all three speed modes, including high-speed mode (3.4 MHz). An external address selection pin allows up to three DAC121C081 or nine DAC121C085 devices per 2-wire bus. Pin compatible alternatives to the DAC121C081 are available that provide additional address options.
The DAC121C081 and DAC121C085 each have a 16-bit register that controls the mode of operation, the power-down condition, and the output voltage. A power-on reset circuit ensures that the DAC output powers up to 0 V. A power-down feature reduces power consumption to less than a microWatt. Their low power consumption and small packages make these DACs an excellent choice for use in battery-operated equipment. Each DAC operates over the extended industrial temperature range of −40°C to +125°C.
The DAC121C081 and DAC121C085 are each part of a family of pin compatible DACs that also provide 8 and 10 bit resolution. For 8-bit DACs see the DAC081C081 and DAC081C085. For 10-bit DACs see the DAC101C081 and DAC101C085.
PIN | TYPE | DESCRIPTION | EQUIVALENT CIRCUIT | |||
---|---|---|---|---|---|---|
NAME | WSON | SOT | VSSOP | |||
ADR0 | 1 | 6 | 1 | Digital Input, three levels |
Tri-state Address Selection Input. Sets the two Least Significant Bits (A1 and A0) of the 7-bit slave address. (see Table 1) |
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ADR1 | — | — | 2 | Digital Input, three levels |
Tri-state Address Selection Input. Sets Bits A6 and A3 of the 7-bit slave address. (see Table 1) | |
GND | 4 | 3 | 5 | Ground | Ground for all on-chip circuitry | — |
SCL | 2 | 5 | 3 | Digital Input | Serial Clock Input. SCL is used together with SDA to control the transfer of data in and out of the device. |
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SDA | 3 | 4 | 4 | Digital Input/Output |
Serial Data bi-directional connection. Data is clocked into or out of the internal 16-bit register relative to the clock edges of SCL. This is an open-drain data line that must be pulled to the supply (VA) by an external pullup resistor. | |
VOUT | 6 | 1 | 8 | Analog Output | Analog Output Voltage | — |
VA | 5 | 2 | 6 | Supply | Power supply input. For the SOT and WSON versions, this supply is used as the reference. Must be decoupled to GND. | — |
VREF | — | — | 7 | Supply | Unbufferred reference voltage. For the VSSOP, this supply is used as the reference. VREF must be free of noise and decoupled to GND. | — |
PAD | (LLP only) | — | — | Ground | Exposed die attach pad can be connected to ground or left floating. Soldering the pad to the PCB offers optimal thermal performance and enhances package self-alignment during reflow. | — |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Supply voltage, VA | –0.3 | 6.5 | V | ||
Voltage on any input pin | –0.3 | 6.5 | V | ||
Input current at any pin(4) | ±10 | mA | |||
Package input current(4) | ±20 | mA | |||
Power consumption at TA = 25°C | See(5) | ||||
Junction temperature, TJ | 150 | °C | |||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
DAC081C081 in NGF Package | |||||
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 | All pins except 2 and 3 | ±2500 | V |
Pins 2 and 3 | ±5000 | ||||
Charged-device model (CDM), per JEDEC specification JESD22-C101 | All pins except 2 and 3 | ±1000 | |||
Pins 2 and 3 | ±1000 | ||||
Machine model (MM) | All pins except 2 and 3 | ±250 | |||
Pins 2 and 3 | ±350 | ||||
DAC081C081 in DDC Package | |||||
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 | All pins except 4 and 5 | ±2500 | V |
Pins 4 and 5 | ±5000 | ||||
Charged-device model (CDM), per JEDEC specification JESD22-C101 | All pins except 4 and 5 | ±1000 | |||
Pins 4 and 5 | ±1000 | ||||
Machine model (MM) | All pins except 4 and 5 | ±250 | |||
Pins 4 and 5 | ±350 | ||||
DAC081C085 in DGK Package | |||||
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 | All pins except 3 and 4 | ±2500 | V |
Pins 3 and 4 | ±5000 | ||||
Charged-device model (CDM), per JEDEC specification JESD22-C101 | All pins except 3 and 4 | ±1000 | |||
Pins 3 and 4 | ±1000 | ||||
Machine model (MM) | All pins except 3 and 4 | ±250 | |||
Pins 3 and 4 | ±350 |
MIN | MAX | UNIT | |
---|---|---|---|
Operating temperature, TA | −40 | 125 | °C |
Supply voltage, VA | 2.7 | 5.5 | V |
Reference voltage, VREFIN | 1 | VA | V |
Digital input voltage(2) | 0 | 5.5 | V |
Output load | 0 | 1500 | pF |
THERMAL METRIC(1)(2)(3) | DAC121C081 | DAC121C085 | UNIT | ||
---|---|---|---|---|---|
NGF (WSON) | DDC (SOT) | DGK (VSSOP) | |||
6 PINS | 6 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 190 | 250 | 240 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP(3) | MAX(3) | UNIT | ||
---|---|---|---|---|---|---|---|
STATIC PERFORMANCE | |||||||
INL | Resolution | 12 | Bits | ||||
Monotonicity | 12 | Bits | |||||
Integral Non-Linearity | 2.2 | 8 | LSB | ||||
–8 | –1.5 | ||||||
DNL | Differential Non-Linearity | 0.18 | 0.6 | LSB | |||
–0.5 | –0.12 | LSB | |||||
ZE | Zero Code Error | IOUT = 0 | 1.1 | 10 | mV | ||
FSE | Full-Scale Error | IOUT = 0 | –0.1 | −0.7 | %FSR | ||
GE | Gain Error | All ones Loaded to DAC register | –0.2 | −0.7 | %FSR | ||
ZCED | Zero Code Error Drift | –20 | µV/°C | ||||
TC GE | Gain Error Tempco | VA = 3 V | –0.7 | ppm FSR/°C | |||
VA = 5 V | –1 | ||||||
ANALOG OUTPUT CHARACTERISTICS (VOUT) | |||||||
Output voltage range(4) | DAC121C085 | 0 | VREF | V | |||
DAC121C081 | 0 | VA | |||||
ZCO | Zero code output | VA = 3 V, IOUT = 200 µA | 1.3 | mV | |||
VA = 5 V, IOUT = 200 µA | 7 | ||||||
FSO | Full scale output | VA = 3 V, IOUT = 200 µA | 2.984 | V | |||
VA = 5 V, IOUT = 200 µA | 4.989 | ||||||
IOS | Output short-circuit current (ISOURCE) |
VA = 3 V, VOUT = 0 V, Input Code = FFFh. |
56 | mA | |||
VA = 5 V, VOUT = 0 V, Input Code = FFFh. |
69 | ||||||
IOS | Output short-circuit current (ISINK) |
VA = 3 V, VOUT = 3 V, Input Code = 000h. |
–52 | mA | |||
VA = 5 V, VOUT = 5 V, Input Code = 000h. |
–75 | ||||||
IO | Continuous output current(4) | Available on the DAC output | 11 | mA | |||
CL | Maximum load capacitance | RL = ∞ | 1500 | pF | |||
RL = 2 kΩ | 1500 | ||||||
ZOUT | DC output impedance | 7.5 | Ω | ||||
REFERENCE INPUT CHARACTERISTICS (DAC121C085 only) | |||||||
VREF | Input range minimum | 1 | 0.2 | V | |||
Input range maximum | VA | V | |||||
Input impedance | 120 | kΩ | |||||
LOGIC INPUT CHARACTERISTICS (SCL, SDA) | |||||||
VIH | Input high voltage | 0.7 × VA | V | ||||
VIL | Input low voltage | 0.3 × VA | V | ||||
IIN | Input current | ±1 | µA | ||||
CIN | Input pin capacitance(4) | 3 | pF | ||||
VHYST | Input hysteresis | 0.1 × VA | V | ||||
LOGIC INPUT CHARACTERISTICS (ADR0, ADR1) | |||||||
VIH | Input high voltage | VA- 0.5 | V | ||||
VIL | Input low voltage | 0.5 | V | ||||
IIN | Input current | ±1 | µA | ||||
LOGIC OUTPUT CHARACTERISTICS (SDA) | |||||||
VOL | Output low voltage | ISINK = 3 mA | 0.4 | V | |||
ISINK = 6 mA | 0.6 | ||||||
IOZ | High-impedence output leakage current | ±1 | µA | ||||
POWER REQUIREMENTS | |||||||
VA | Supply voltage minimum | 2.7 | V | ||||
Supply voltage maximum | 5.5 | ||||||
Normal -- VOUT set to midscale. 2-wire interface quiet (SCL = SDA = VA). (output unloaded) | |||||||
IST_VA-1 | VADAC121C081 supply current | VA = 2.7 V to 3.6 V | 105 | 156 | µA | ||
VA = 4.5 V to 5.5 V | 132 | 214 | |||||
IST_VA-5 | VADAC121C085 supply current | VA = 2.7 V to 3.6 V | 86 | 118 | µA | ||
VA = 4.5 V to 5.5 V | 98 | 152 | |||||
IST_VREF | VREF supply current (DAC121C085 only) |
VA = 2.7 V to 3.6 V | 37 | 43 | µA | ||
VA = 4.5 V to 5.5 V | 53 | 61 | |||||
PST | Power consumption (VA and VREF for DAC121C085)(2) |
VA = 3 V | 380 | µW | |||
VA = 5 V | 730 | ||||||
Continuous Operation -- 2-wire interface actively addressing the DAC and writing to the DAC register. (output unloaded) | |||||||
ICO_VA-1 | VADAC121C081 supply current | fSCL=400 kHz | VA = 2.7 V to 3.6 V | 134 | 220 | µA | |
VA = 4.5 V to 5.5 V | 192 | 300 | |||||
fSCL = 3.4 MHz | VA = 2.7 V to 3.6 V | 225 | 320 | µA | |||
VA = 4.5 V to 5.5 V | 374 | 500 | |||||
ICO_VA-5 | VADAC121C085 supply current | fSCL = 400 kHz | VA = 2.7 V to 3.6 V | 101 | 155 | µA | |
VA = 4.5 V to 5.5 V | 142 | 220 | |||||
fSCL = 3.4 MHz | VA = 2.7 V to 3.6 V | 193 | 235 | µA | |||
VA = 4.5 V to 5.5 V | 325 | 410 | |||||
ICO_VREF | VREF supply current (DAC121C085 only) |
VA = 2.7 V to 3.6 V | 33.5 | 55 | µA | ||
VA = 4.5 V to 5.5 V | 49.5 | 71.4 | |||||
PCO | Power consumption (VA and VREF for DAC121C085) |
fSCL = 400 kHz | VA = 3 V | 480 | µW | ||
VA = 5 V | 1.06 | mW | |||||
fSCL = 3.4 MHz | VA = 3 V | 810 | µW | ||||
VA = 5 V | 2.06 | mW | |||||
Power Down -- 2-wire interface quiet (SCL = SDA = VA) after PD mode written to DAC register. (output unloaded) | |||||||
IPD | Supply current (VA and VREF for DAC121C085) |
All power-down modes | VA = 2.7 V to 3.6 | 0.13 | 1.52 | µA | |
VA = 4.5 V to 5.5 V | 0.15 | 3.25 | |||||
PPD | Power consumption (VA and VREF for DAC121C085) |
All power-down modes | VA = 3 V | 0.5 | µW | ||
VA = 5 V | 0.9 |
PARAMETER | TEST CONDITIONS(7) | MIN | TYP(3) | MAX(7)(3) | UNIT | ||
---|---|---|---|---|---|---|---|
ts | Output Voltage Settling Time(4) | 400h to C00h code change RL = 2 kΩ, CL = 200 pF |
6 | 8.5 | µs | ||
SR | Output Slew Rate | 1 | V/µs | ||||
Glitch Impulse | Code change from 800h to 7FFh | 12 | nV-sec | ||||
Digital Feedthrough | 0.5 | nV-sec | |||||
Multiplying Bandwidth(6) | VREF = 2.5 V ± 0.1 Vpp | 160 | kHz | ||||
Total Harmonic Distortion(6) | VREF = 2.5 V ± 0.1 Vpp input frequency = 10 kHz |
70 | dB | ||||
tWU | Wake-Up Time | VA = 3 V | 0.8 | µs | |||
VA = 5 V | 0.5 | µs | |||||
DIGITAL TIMING SPECS (SCL, SDA) | |||||||
fSCL | Serial Clock Frequency | Standard Mode | 100 | kHz | |||
Fast Mode | 400 | ||||||
High Speed Mode, Cb = 100 pF | 3.4 | MHz | |||||
High Speed Mode, Cb = 400 pF | 1.7 | ||||||
tLOW | SCL Low Time | Standard Mode | 4.7 | µs | |||
Fast Mode | 1.3 | ||||||
High Speed Mode, Cb = 100 pF | 160 | ns | |||||
High Speed Mode, Cb = 400 pF | 320 | ||||||
tHIGH | SCL High Time | Standard Mode | 4 | µs | |||
Fast Mode | 0.6 | ||||||
High Speed Mode, Cb = 100 pF | 60 | ns | |||||
High Speed Mode, Cb = 400 pF | 120 | ||||||
tSU;DAT | Data Setup Time | Standard Mode | 250 | ns | |||
Fast Mode | 100 | ||||||
High Speed Mode | 10 | ||||||
tHD;DAT | Data Hold Time | Standard Mode | 0 | 3.45 | µs | ||
Fast Mode | 0 | 0.9 | |||||
High Speed Mode, Cb = 100 pF | 0 | 70 | ns | ||||
High Speed Mode, Cb = 400 pF | 0 | 150 | |||||
tSU;STA | Setup time for a start or a repeated start condition | Standard Mode | 4.7 | µs | |||
Fast Mode | 0.6 | ||||||
High Speed Mode | 160 | ns | |||||
tHD;STA | Hold time for a start or a repeated start condition | Standard Mode | 4 | µs | |||
Fast Mode | 0.6 | ||||||
High Speed Mode | 160 | ns | |||||
tBUF | Bus free time between a stop and start condition | Standard Mode | 4.7 | µs | |||
Fast Mode | 1.3 | ||||||
tSU;STO | Setup time for a stop condition | Standard Mode | 4 | µs | |||
Fast Mode | 0.6 | ||||||
High Speed Mode | 160 | ns | |||||
trDA | Rise time of SDA signal | Standard Mode | 1000 | ns | |||
Fast Mode | 20+0.1Cb | 300 | |||||
High Speed Mode, Cb = 100 pF | 10 | 80 | |||||
High Speed Mode, Cb = 400 pF | 20 | 160 | |||||
tfDA | Fall time of SDA signal | Standard Mode | 250 | ns | |||
Fast Mode | 20+0.1Cb | 250 | |||||
High Speed Mode, Cb = 100 pF | 10 | 80 | |||||
High Speed Mode, Cb = 400 pF | 20 | 160 | |||||
trCL | Rise time of SCL signal | Standard Mode | 1000 | ns | |||
Fast Mode | 20+0.1Cb | 300 | |||||
High Speed Mode, Cb = 100 pF | 10 | 40 | |||||
High Speed Mode, Cb = 400 pF | 20 | 80 | |||||
trCL1 | Rise time of SCL signal after a repeated start condition and after an acknowledge bit. | Standard Mode | 1000 | ns | |||
Fast Mode | 20+0.1Cb | 300 | |||||
High Speed Mode, Cb = 100 pF | 10 | 80 | |||||
High Speed Mode, Cb = 400 pF | 20 | 160 | |||||
tfCL | Fall time of a SCL signal | Standard Mode | 300 | ns | |||
Fast Mode | 20+0.1Cb | 300 | |||||
High Speed Mode, Cb = 100 pF | 10 | 40 | |||||
High Speed Mode, Cb = 400 pF | 20 | 80 | |||||
Cb | Capacitive load for each bus line (SCL and SDA) | 400 | pF | ||||
tSP | Pulse Width of spike suppressed(5)(4) | Fast Mode | 50 | ns | |||
High Speed Mode | 10 | ||||||
toutz | SDA output delay (see the Additional Timing Information section) | Fast Mode | 87 | 270 | ns | ||
High Speed Mode | 38 | 60 |