The DAC3174 is a dual-channel, 14-bit, 500-MSPS, digital-to-analog converter (DAC). The DAC3174 uses a 14-bit, low-voltage differential signaling (LVDS) digital bus, with one or two independent dual-data rate (DDR) data clocks for flexibility in providing data from different sources in each channel.
An input first-in first out block (FIFO) allows independent data and sample clocks. FIFO input and output pointers can be synchronized across multiple devices for precise signal synchronization.
The DAC outputs are current sourcing and terminate to GND with a compliance range of –0.5 V to +1 V.
The DAC3174 is pin compatible with the dual-channel, 500-MSPS, 12-bit DAC3164 and 10-bit DAC3154, and the single-channel, 500-MSPS, 14-bit DAC3171, 12-bit DAC3161, and 10-bit DAC3151.
The device is available in a 64-pin VQFN PowerPAD™ package. and is specified over the full industrial temperature range of –40°C to +85°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DAC3174 | VQFN (64) | 9.00 mm × 9.00 mm |
Changes from A Revision (May 2013) to B Revision
Changes from * Revision (April 2013) to A Revision
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage | VDDA33 to GND | –0.5 | 4 | V |
VDDA18 to GND | –0.5 | 2.3 | ||
CLKVDD18 to GND | –0.5 | 2.3 | ||
IOVDD to GND | –0.5 | 4 | ||
DIGVDD18 to GND | –0.5 | 2.3 | ||
Terminal voltage | CLKVDD18 to DIGVDD18 | –0.5 | 0.5 | V |
VDDA18 to DIGVDD18 | –0.5 | 0.5 | ||
DA[6:0]P, DA[6:0]N, DB[6:0]P, DB[6:0]N, D[13:0]P, D[13:0]N, DATACLKP, DATACLKN, DA_CLKP, DA_CLKPN, DB_CLKP, DB_CLKN, SYNCP, SYNCN to GND | –0.5 | DIGVDD18 + 0.5 | ||
DACCLKP, DACCLKN, ALIGNP, ALIGNN | –0.5 | CLKVDD18 + 0.5 | ||
TXENABLE, ALARM, SDO, SDIO, SCLK, SDENB, RESETB to GND | –0.5 | IOVDD + 0.5 | ||
IOUTAP, IOUTAN, IOUTBP, IOUTBN to GND | –0.7 | 1.4 | ||
EXTIO, BIASJ to GND | –0.5 | VDDA33 + 0.5 | ||
Temperature | Operating ambient free-air, TA | –40 | 85 | °C |
Maximum junction, TJ | 125 | |||
Storage, Tstg | –65 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
CLKVDD18 | Clock buffer supply | 1.71 | 1.8 | 1.89 | V |
DIGVDD18 | Digital supply | 1.71 | 1.8 | 1.89 | V |
VDDA18 | 1.8-V analog supply | 1.71 | 1.8 | 1.89 | V |
VFUSE | Fuse bank supply | 1.71 | 1.8 | 1.89 | V |
IOVDD | IO supply(1) | 1.71 | 3.45 | V | |
VDDA33 | 3.3-V analog supply | 3.15 | 3.3 | 3.45 | V |
TA | Operating ambient free-air temperature | –40 | 25 | 85 | °C |
TJ | Operating junction temperature(2) | 105 | °C |
THERMAL METRIC(1) | DAC3174 | UNIT | |
---|---|---|---|
RGC (VQFN) | |||
64 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 23 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 7.6 | °C/W |
RθJB | Junction-to-board thermal resistance | 2.8 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.1 | °C/W |
ψJB | Junction-to-board characterization parameter | 2.8 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 0.2 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Resolution | 14 | Bits | ||||
DC ACCURACY | ||||||
DNL | Differential nonlinearity | 1 LSB = IOUTFS / 214 | ±1 | LSB | ||
INL | Integral nonlinearity | 1 LSB = IOUTFS / 214 | ±2 | LSB | ||
ANALOG OUTPUTS | ||||||
Coarse gain linearity | ±0.4 | LSB | ||||
Offset error | Midcode offset | 0.01 | %FSR | |||
Gain error | With external reference | ±2 | %FSR | |||
With internal reference | ±2 | |||||
Gain mismatch | With internal reference | –2 | 2 | %FSR | ||
Minimum full-scale output current | Nominal full-scale current, IOUTFS = 16 × IBAIS current |
2 | mA | |||
Maximum full-scale output current | Nominal full-scale current, IOUTFS = 16 × IBAIS current |
20 | mA | |||
Output compliance | IOUTFS = 20 mA | –0.5 | 1 | V | ||
Output resistance | 300 | kΩ | ||||
Output capacitance | 5 | pF | ||||
REFERENCE OUTPUT | ||||||
VREF | Reference output voltage | 1.14 | 1.2 | 1.26 | V | |
Reference output current | 100 | nA | ||||
REFERENCE INPUT | ||||||
VEXTIO input voltage | External reference mode | 0.1 | 1.2 | 1.25 | V | |
Input resistance | 1 | MΩ | ||||
Small-signal bandwidth | 500 | kHz | ||||
Input capacitance | 100 | pF | ||||
TEMPERATURE COEFFICIENTS | ||||||
Offset drift | ±1 | ppm of FSR/°C | ||||
Gain drift | With external reference | ±15 | ||||
With internal reference | ±30 | |||||
Reference voltage drift | ±8 | ppm /°C | ||||
POWER CONSUMPTION | ||||||
IVDDA33 | 3.3-V analog supply current | MODE 1, fDAC = 491.52 MSPS, QMC on, IF = 20 MHz | 52 | 59 | mA | |
MODE 2, fDAC = 320 MSPS, QMC on, IF = 20 MHz |
51 | |||||
MODE 3, sleep mode, fDAC = 491.52 MSPS, DAC in sleep mode | 2.6 | |||||
MODE 4, power-down mode, no clock, DAC in sleep mode | 1.6 | 4 | ||||
ICLKVDD18 | 1.8-V clock and analog supply current (CLKVDD18 and VDDA18) | MODE 1, fDAC = 491.52 MSPS, QMC on, IF = 20 MHz | 49 | 57 | mA | |
MODE 2, fDAC = 320 MSPS, QMC on, IF = 20 MHz |
38 | |||||
MODE 3, sleep mode, fDAC = 491.52 MSPS, DAC in sleep mode | 43 | |||||
MODE 4, power-down mode, no clock, DAC in sleep mode | 1.8 | 4 | ||||
IDIGVDD18 | 1.8-V digital supply current (DIGVDD18 and VFUSE) |
MODE 1, fDAC = 491.52 MSPS, QMC on, IF = 20 MHz | 115 | 130 | mA | |
MODE 2, fDAC = 320 MSPS, QMC on, IF = 20 MHz |
87 | |||||
MODE 3, sleep mode, fDAC = 491.52 MSPS, DAC in sleep mode | 110 | |||||
MODE 4, power-down mode, no clock, DAC in sleep mode | 0.7 | 3 | ||||
IIOVDD | 1.8-V IO supply current | MODE 1, fDAC = 491.52 MSPS, QMC on, IF = 20 MHz | 0.002 | 0.015 | mA | |
MODE 2, fDAC = 320 MSPS, QMC on, IF = 20 MHz |
0.002 | |||||
MODE 3, sleep mode, fDAC = 491.52 MSPS, DAC in sleep mode | 0.003 | |||||
MODE 4, power-down mode, no clock, DAC in sleep mode | 0.003 | 0.015 | ||||
Pdis | Total power dissipation | MODE 1, fDAC = 491.52 MSPS, QMC on, IF = 20 MHz | 464 | 530 | mW | |
MODE 2, fDAC = 320 MSPS, QMC on, IF = 20 MHz |
396 | |||||
MODE 3, sleep mode, fDAC = 491.52 MSPS, DAC in sleep mode | 284 | |||||
MODE 4, power-down mode, no clock, DAC in sleep mode | 10 | 26 | ||||
PSRR | Power-supply rejection ratio | DC tested | –0.4 | 0.4 | %FSR/V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG OUTPUT | ||||||
fDAC | Maximum sample rate | 500 | MSPS | |||
ts(DAC) | Output settling time to 0.1% | Transition: Code 0x0000 to 0x3FFF | 11 | ns | ||
tPD | Output propagation delay | Does not include digital latency | 2 | ns | ||
tr(IOUT) | Output rise time | 10% to 90% | 200 | ps | ||
tf(IOUT) | Output fall time | 90% to 10% | 200 | ps | ||
Digital latency | Length of delay from DAC pin inputs to DATA at output pins. In normal operation mode including the latency of FIFO. | 26 | DACCLK | |||
AC PERFORMANCE | ||||||
SFDR | Spurious free dynamic | fDAC = 500 MSPS, fout = 10.1 MHz | 82 | dBc | ||
fDAC = 500 MSPS, fout = 20.1 MHz | 78 | |||||
fDAC = 500 MSPS, fout = 70.1 MHz | 74 | |||||
IMD3 | Intermodulation distortion | fDAC = 500 MSPS, fout = 10.1 ±0.5 MHz | 84 | dBc | ||
fDAC = 500 MSPS, fout = 20.1 ±0.5 MHz | 84 | |||||
fDAC = 500 MSPS, fout = 70.1 ±0.5 MHz | 75 | |||||
fDAC = 500 MSPS, fout = 150.1 ±0.5 MHz | 63 | |||||
NSD | Noise spectral density | fDAC = 500 MSPS, fout = 10.1 MHz | 160 | dBc/Hz | ||
fDAC = 500 MSPS, fout = 20.1 MHz | 157 | |||||
fDAC = 500 MSPS, fout = 70.1 MHz | 155 | |||||
ACLR | Adjacent channel leakage ratio | fDAC = 491.52 MSPS, fout = 30.72 MHz, WCDMA TM1 | 78 | dBc | ||
f AC = 491.52 MSPS, fout = 153.6 MHz, WCDMA TM1 | 74 |
PARAMETERS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
CMOS DIGITAL INPUTS (RESETB, SDENB, SCLK, SDIO, TXENABLE) | ||||||||
VIH | High-level input voltage | IOVDD = 3.3 V, 2.5 V, or 1.8 V | IOVDD × 0.6 | V | ||||
VIL | Low-level input voltage | IOVDD = 3.3 V, 2.5 V, or 1.8 V | 0.25 × IOVDD | V | ||||
IIH | High-level input current | IOVDD = 3.3 V, 2.5 V, or 1.8 V | –40 | 40 | µA | |||
IIL | Low-level input current | IOVDD = 3.3 V, 2.5 V, or 1.8 V | –40 | 40 | µA | |||
DIGITAL OUTPUTS – CMOS INTERFACE (SDOUT, SDIO) | ||||||||
VOH | High-level output voltage | IOVDD = 3.3 V, 2.5 V, or 1.8 V | 0.85 × IOVDD | V | ||||
VOL | Low-level output voltage | 0.125 × IOVDD | V | |||||
LVPECL INPUTS – (DACCLKx, ALIGNx) | ||||||||
VCM | LVPECL input common-mode voltage | 0.5 | V | |||||
VIDIFF | Differential input peak-to-peak voltage | 0.4 | 1 | V | ||||
LVDS INTERFACE (DATA[13:0]x, DA[6:0]x , DB[6:0]x , DA_CLKx, DB_CLKx, DATACLKx, SYNCx) | ||||||||
VA,B+ | Logic high differential input voltage threshold | 175 | mV | |||||
VA,B– | Logic low differential input voltage threshold | –175 | mV | |||||
VCOM | LVDS input common-mode voltage | 1 | 1.2 | 2 | V | |||
ZT | Internal termination | 85 | 110 | 135 | Ω | |||
CL | LVDS input capacitance | 2 | pF |
MIN | TYP | MAX | UNIT | |||||
---|---|---|---|---|---|---|---|---|
SERIAL PORT TIMING | ||||||||
ts(SENDB) | Setup time, SDENB to rising edge of SCLK | 20 | ns | |||||
ts(SDIO) | Setup time, SDIO to rising edge of SCLK | 10 | ns | |||||
th(SDIO) | Hold time, SDIO from rising edge of SCLK | 5 | ns | |||||
t(SCLK) | Period of SCLK | 100 | ns | |||||
t(SCLKH) | High time of SCLK | 40 | ns | |||||
t(SCLKL) | Low time of SCLK | 40 | ns | |||||
td(DATA) | Data output delay after falling edge of SCLK | 10 | ns | |||||
TRESET | Minimum RESTB pulse duration | 25 | ns | |||||
LVDS INPUT TIMING | ||||||||
ts(DATA) | Setup time | D[x..0] valid to DATACLK rising or falling edge for single bus single clock mode ; DA/DB[x…0] valid to DB_CLK rising or falling edge for dual bus single clock mode; DA[x..0] valid to DA_CLK rising or falling edge, and DB[x…0] valid for DB_CLK rising or falling edge for dual bus dual clock mode |
config3 Setting | ps | ||||
datadly | clkdly | |||||||
0 | 0 | –20 | ||||||
0 | 1 | –120 | ||||||
0 | 2 | –220 | ||||||
0 | 3 | –310 | ||||||
0 | 4 | –390 | ||||||
0 | 5 | –480 | ||||||
0 | 6 | –560 | ||||||
0 | 7 | –630 | ||||||
1 | 0 | 70 | ||||||
2 | 0 | 150 | ||||||
3 | 0 | 230 | ||||||
4 | 0 | 330 | ||||||
5 | 0 | 430 | ||||||
6 | 0 | 530 | ||||||
7 | 0 | 620 | ||||||
th(DATA) | Hold time | D[x..0] valid to DATACLK rising or falling edge for single bus single clock mode; DA/DB[x…0] valid to DB_CLK rising or falling edge for dual bus single clock mode; DA[x..0] valid to DA_CLK rising or falling edge, and DB[x…0] valid for DB_CLK rising or falling edge for dual bus dual clock mode. |
config3 Setting | ps | ||||
datadly | clkdly | |||||||
0 | 0 | 310 | ||||||
0 | 1 | 390 | ||||||
0 | 2 | 480 | ||||||
0 | 3 | 560 | ||||||
0 | 4 | 650 | ||||||
0 | 5 | 740 | ||||||
0 | 6 | 850 | ||||||
0 | 7 | 930 | ||||||
1 | 0 | 200 | ||||||
2 | 0 | 100 | ||||||
3 | 0 | 20 | ||||||
4 | 0 | –60 | ||||||
5 | 0 | –140 | ||||||
6 | 0 | –220 | ||||||
7 | 0 | –290 |
IF = 20 MHz |
IF = 20 MHz |
IF = 70 MHz |
IF = 70 MHz |
The DAC3174 device is a dual-channel, 14-bit, 500-MSPS, digital-to-analog converter (DAC), and uses a 14-bit, wide LVDS digital bus with an input FIFO. The data for the two channels are multiplexed onto the 14-bit LVDS bus in a dual-data-rate (DDR) fashion. The DAC3174 also supports a DDR, 7-bit, LVDS interface mode for each channel.
The DAC3174 has separate input data clock for the digital data and sample clock for the analog output. The FIFO input and output pointers can be synchronized across multiple devices for precise signal synchronization. The DAC outputs are current sourcing and terminate to GND with a compliance range of –0.5 V to +1 V. The DAC3174 is pin-compatible with the 12-bit DAC3164 and 10-bit DAC3154. as well as the single-channel DAC31x1 family.
The DAC3174 includes flexible alarm monitoring that can be used to alert a possible malfunction scenario. All alarm events can be accessed either through the SIP registers and through the ALARM pin. After an alarm is set, the corresponding alarm bit in register config5 must be reset through the serial interface in order to allow further testing. The set of alarms includes the following conditions:
To prevent unexpected DAC outputs from propagating into the transmit channel chain, the DAC3174 includes a feature that disables the outputs when a catastrophic alarm occurs. The catastrophic alarms include FIFO pointer collision, the loss DACCLK, or the loss of DATACLK. When any of these alarms occur, the internal TXenable signal is driven low and causes a zeroing of the data going to the DAC in < 10 T, where T = DACCLK period. One caveat is that if both clocks stop, the circuit cannot determine clock loss, so no alarms are generated; therefore, no zeroing of output data occurs.
Table 1 through Table 4 list the single and dual bus clock modes of the DAC3174.
DIFFERENTIAL PAIR (P/N) | BITS | |
---|---|---|
DATACLK RISING EDGE | DATACLK FALLING EDGE | |
D13 | A13 | B13 |
D12 | A12 | B12 |
D11 | A11 | B11 |
D10 | A10 | B10 |
D9 | A9 | B9 |
D8 | A8 | B8 |
D7 | A7 | B7 |
D6 | A6 | B6 |
D5 | A5 | B5 |
D4 | A4 | B4 |
D3 | A3 | B3 |
D2 | A2 | B2 |
D1 | A1 | B1 |
D0 | A0 | B0 |
SYNC | FIFO Write Reset | — |
DIFFERENTIAL PAIR (P/N) | BITS | |
---|---|---|
DATACLK RISING EDGE | DATACLK FALLING EDGE | |
D13 | A13 | — |
D12 | A12 | — |
D11 | A11 | — |
D10 | A10 | — |
D9 | A9 | — |
D8 | A8 | — |
D7 | A7 | — |
D6 | A6 | — |
D5 | A5 | — |
D4 | A4 | — |
D3 | A3 | — |
D2 | A2 | — |
D1 | A1 | — |
D0 | A0 | — |
SYNC | FIFO Write Reset | — |
DIFFERENTIAL PAIR (P/N) | DB_CLK RISING EDGE | DB_CLK FALLING EDGE |
---|---|---|
DA6 | A13 | A6 |
DA5 | A12 | A5 |
DA4 | A11 | A4 |
DA3 | A10 | A3 |
DA2 | A9 | A2 |
DA1 | A8 | A1 |
DA0 | A7 | A0 |
DB6 | B13 | B6 |
DB5 | B12 | B5 |
DB4 | B11 | B4 |
DB3 | B10 | B3 |
DB2 | B9 | B2 |
DB1 | B8 | B1 |
DB0 | B7 | B0 |
SYNC | FIFO Write Reset | — |
DIFFERENTIAL PAIR (P/N) | DA_CLK RISING EDGE | DA_CLK FALLING EDGE |
---|---|---|
DA6 | A13 | A6 |
DA5 | A12 | A5 |
DA4 | A11 | A4 |
DA3 | A10 | A3 |
DA2 | A9 | A2 |
DA1 | A8 | A1 |
DA0 | A7 | A0 |
— | DB_CLK RISING EDGE | DB_CLK FALLING EDGE |
DB6 | B13 | B6 |
DB5 | B12 | B5 |
DB4 | B11 | B4 |
DB3 | B10 | B3 |
DB2 | B9 | B2 |
DB1 | B8 | B1 |
DB0 | B7 | B0 |
NOTE
When rev (config0, bit 11) is asserted, the MSB through the LSB of the input bits are reversed. When using the 14-bit interface, all 14 bits are reversed as one word; when using the 7-bit interface, each of the 7 bits are reversed.
There are three modes of syncing included in the DAC3174:
NOTE
When ALIGNP and ALIGNN are not used, TI recommends clearing alignrx_ena (config 1, bit 4), tying ALIGNP to DIGVDD18, and tying ALIGNN to ground. When SYNCP and SYNCN are not used, TI recommends clearing syncrx_ena (config 0, bit 3). Then, the unused SYNCP and SYNCN pins can be left open or tied to ground.
The following startup sequence is recommended to power-up the DAC3174:
The serial port of the DAC3174 is a flexible serial interface that communicates with industry-standard microprocessors and microcontrollers. The interface provides read or write access to all registers used to define the operating modes of DAC3174. The interface is compatible with most synchronous transfer formats and can be configured as a 3- or 4-pin interface by sif4_ena (register config0, bit 9). In both configurations, SCLK is the serial interface input clock, and SDENB is serial interface enable. For 3-pin configuration, SDIO is a bidirectional pin for both data in and data out. For 4-pin configuration, SDIO is data in only, and SDO is data out only. Data are input into the device with the rising edge of SCLK. Data are output from the device on the falling edge of SCLK.
Each read or write operation is framed by signal SDENB (serial data enable bar) asserted low. The first frame byte is the instruction cycle that identifies the following data transfer cycle as read or write, as well as the 7-bit address to be accessed. Table 1 indicates the function of each bit in the instruction cycle, and is followed by a detailed description of each bit. The data transfer cycle consists of two bytes.
MSB | LSB |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Description | R/W | A6 | A5 | A4 | A3 | A2 | A1 | A0 |
R/W | Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation from the DAC3174, and a low indicates a write operation to the DAC3174. |
[A6:A0] | Identifies the address of the register to be accessed during the read or write operation. |
Figure 27 shows the serial interface timing diagram for a DAC3174 write operation. SCLK is the serial interface clock input to the DAC3174. Serial data enable SDENB is an active low input to the DAC3174. SDIO is serial data in. Input data to the DAC3174 is clocked on the rising edges of SCLK.
Figure 28 shows the serial interface timing diagram for a DAC3174 read operation. SCLK is the serial interface clock input to the DAC3174. Serial data enable SDENB is an active low input to the DAC3174. SDIO is serial data in during the instruction cycle. In 3-pin configuration, SDIO is data out from the DAC3174 during the data transfer cycle, while SDO is in a high-impedance state. In 4-pin configuration, both SDIO and SDO are data out from the DAC3174 during the data transfer cycle. At the end of the data transfer, SDIO and SDO output low on the final falling edge of SCLK until the rising edge of SDENB when they become high impedance.
Table 5 lists the register maps for the DAC3174.
In the SIF interface, there are three types of registers:
NAME | ADDR (HEX) | DEFAULT | BIT 15 (MSB) |
BIT 14 | BIT 13 | BIT 12 | BIT 11 | BIT 10 | BIT 9 | BIT 8 | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 (LSB) |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
config0 | 0x00 | 0x44FC | qmc_ offset_ena | dual_ ena | chipwidth (1:0) | rev | twos | sif4_ ena | reserved | fifo_ ena | alarm_ out_ena | alarm_ out_pol | alignrx_ ena | syncrx_ ena | lvdsdataclk _ena | reserved | synconly_ena | |
config1 | 0x01 | 0x600E | iotest_ena | bsideclk_ ena | fullword_ interface_ ena | 64cnt_ ena | dacclk_gone_ ena | dataclkgone _ena | collision_ ena | reserved | daca_ compliment | dacb_ compliment | sif_ sync | sif_ sync_ena | alarm_ 2away_ ena | alarm_ 1away_ ena | alarm _collision _ena | reserved |
config2 | 0x02 | 0x3FFF | reserved | lvdsdata_ena (13:0) | ||||||||||||||
config3 | 0x03 | 0x0000 | datadlya (2:0) | clkdlya (2:0) | datadlyb (2:0) | clkdlyb (2:0) | extref _ena | reserved | dual_ ena | |||||||||
config4 | 0x04 | 0x0000 | reserved | iotest_results (13:0) | ||||||||||||||
config5 | 0x05 | 0x0000 | alarm_ from_ zerochka | alarm_ from_ zerochkb | alarms_from_fifoa (2:0) | alarms_from_fifob (2:0) | alarm_ dacclk_ gone | alarm_ dataclk_ gone | clock_ gone | alarm_ from_ iotesta | alarm_ from_ iotestb | reserved | ||||||
config6 | 0x06 | 0x0000 | tempdata (7:0) | fuse_cntl (5:0) | reserved | |||||||||||||
config7 | 0x07 | 0xFFFF | alarms_mask (15:0) | |||||||||||||||
config8 | 0x08 | 0x4000 | reserved | qmc_offseta (12:0) | ||||||||||||||
config9 | 0x09 | 0x8000 | fifo_offset (2:0) | qmc_offsetb (12:0) | ||||||||||||||
config10 | 0x0A | 0xF080 | coarse_dac (3:0) | fuse_ sleep | reserved | reserved | tsense_ sleep | clkrecv_ ena | sleepa | sleepb | reserved | |||||||
config11 | 0x0B | 0x1111 | reserved | reserved | reserved | reserved | ||||||||||||
config12 | 0x0C | 0x3A7A | reserved | iotest_pattern0 (13:0) | ||||||||||||||
config13 | 0x0D | 0x36B6 | reserved | iotest_pattern1 (13:0) | ||||||||||||||
config14 | 0x0E | 0x2AEA | reserved | iotest_pattern2 (13:0) | ||||||||||||||
config15 | 0x0F | 0x0545 | reserved | iotest_pattern3 (13:0) | ||||||||||||||
config16 | 0x10 | 0x0585 | reserved | iotest_pattern4 (13:0) | ||||||||||||||
config17 | 0x11 | 0x0949 | reserved | iotest_pattern5 (13:0) | ||||||||||||||
config18 | 0x12 | 0x1515 | reserved | iotest_pattern6 (13:0) | ||||||||||||||
config19 | 0x13 | 0x3ABA | reserved | iotest_pattern7 (13:0) | ||||||||||||||
config20 | 0x14 | 0x0000 | sifdac_ ena | reserved | sifdac (13:0) | |||||||||||||
config21 | 0x15 | 0xFFFF | sleepcntl (15:0) | |||||||||||||||
config22 | 0x16 | 0x0000 | fa002_data(15:0) | |||||||||||||||
config23 | 0x17 | 0x0000 | fa002_data(31:16) | |||||||||||||||
config24 | 0x18 | 0x0000 | fa002_data(47:32) | |||||||||||||||
config25 | 0x19 | 0x0000 | fa002_data(63:48) | |||||||||||||||
config127 | 0x7F | 0x0049 | reserved | reserved | reserved | reserved | reserved | titest_voh | titest_vol | vendorid (1:0) | versionid (2:0) |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
qmc_offset_ena | dual_ena | chipwidth1 | chipwidth0 | rev | twos | sif4_ena | reserved |
R/W-0 | R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-1 | R/W-0 | R/W-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
fifo_ena | alarm_out_ena | alarm_out_pol | alignrx_ena | syncrx_ena | lvdsdataclk_ena | reserved | synconly_ena |
R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config0 | 0x00 | 15 | qmc_offset_ena | Enable the offset function when asserted. | 0 |
14 | dual_ena | Uses both DACs when asserted. | 1 (FUSE controlled) |
||
13:12 | chipwidth | Programmable bits for setting the input interface width: 00: all 14 bits are used 01: upper 12 bits are used 10: upper 10 bits are used 11: upper 10 bits are used. |
00 | ||
11 | rev | Reverses the input bits. When using the 7-bit interface, this reverse each 7-bit input, however when using the 14-bit interface, all 14-bits are reversed as one word. | 0 | ||
10 | twos | When asserted, this bit tells the chip to presume 2's complement data are arriving at the input. Otherwise offset binary is presumed. | 1 | ||
9 | sif4_ena | When asserted the SIF interface becomes a 4-pin interface. This bit has a lower priority than the dieid_ena bit. | 0 | ||
8 | reserved | Reserved | 0 | ||
7 | fifo_ena | When asserted, the FIFO is absorbing the difference between INPUT clock and DAC clock. If it is not asserted then the FIFO buffering is bypassed but the reversing of bits and handling of offset binary input is still available. NOTE: When the FIFO is bypassed the DACCLK and DATACLK must be aligned or there may be timing errors; and, it is not recommended for actual application use. | 1 | ||
6 | alarm_out_ena | When asserted the pin alarm becomes an output instead of a tri-state pin. | 1 | ||
5 | alarm_out_pol | This bit changes the polarity of the ALARM signal (0 = negative logic, 1 = positive logic). | 1 | ||
4 | alignrx_ena | When asserted the ALIGN pin receiver is powered up. NOTE: TI recommends clearing this bit when ALIGNP/N are not used (dual bus mode, and SYNC ONLY and SIF_SYNC modes in single bus mode). | 1 | ||
3 | syncrx_ena | When asserted the SYNC pin receiver is powered up NOTE: TI recommends clearing this bit when SYNCP/N are not used (dual bus mode, and SIF_SYNC mode in single bus mode). | 1 | ||
2 | lvdsdataclk_ena | When asserted the DATACLK pin receiver is powered up. | 1 | ||
1 | reserved | Reserved | 0 | ||
0 | synconly_ena | When asserted the chip is put into the SYNC ONLY mode where the SYNC ONLY pin is used as the sync input for both the front and back of the FIFO. | 0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
iotest_ena | bsideclk_ena | fullwordinterface _ena | 64cnt_ena | dacclkgone_ ena | dataclkgone_ ena | collision_ena | reserved |
R/W-0 | R/W-1 | R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
daca_ compliment | dacb_ compliment | sif_sync | sif_sync_ena | alarm_2away_ ena | alarm_1away_ ena | alarm_collision_ena | reserved |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-1 | R/W-1 | R/W-1 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config1 | 0x01 | 15 | iotest_ena | Turns on the io-testing circuitry when asserted. This is the circuitry that compares an 8-sample input pattern to SIF programmed registers to make sure the data coming into the chip meets setup and hold requirements. If this bit is a 0 then the clock to this circuitry is turned off for power savings. NOTE: Sample 0 must be aligned with the rising edge of SYNC. | 0 |
14 | bsideclk_ena | When asserted the input clock for the B side datapath is enabled. Otherwise the IOTEST and the FIFO on the B-side of the design does not get a clock. | 1 | ||
13 | fullwordinterface_ena | When asserted the input interface is changed to use the full 14-bits for each word, instead of dual, 7-bit buses for two half-words. | 1 | ||
12 | 64cnt_ena | This enables the resetting of the alarms after 64 good samples with the goal of removing unnecessary errors. For instance on a lab board, when checking the setup and hold through IOTEST, there may initially be errors, but once the test is up and running everything works. Setting this bit removes the requirement for a SIF write to clear the alarm register. | 0 | ||
11 | dacclkgone_ena | This allows the DACCLK gone signal from the clock monitor to be used to shut the output off. | 0 | ||
10 | dataclkgone_ena | This allows the DATACLK gone signal from the clock monitor to be used to shut the output off. | 0 | ||
9 | collision_ena | This allows the collision alarm from the FIFO to shut the output off. | 0 | ||
8 | reserved | Reserved | 0 | ||
7 | daca_compliment | When asserted the output to the DACA is complimented. This allows the user of the chip to effectively change the + and – designations of the DAC output pins. | 0 | ||
6 | dacb_compliment | When asserted the output to the DACB is complimented. This allows the user of the chip to effectively change the + and – designations of the DAC output pins. | 0 | ||
5 | sif_sync | This is the SIF_SYNC signal. Whatever is programmed into this bit is used as the chip sync when SIF_SYNC mode is enabled.Design is sensitive to rising edges so programming from 0 → 1 is when the sync pulse is generated. 1 → 0 has no effect. | 0 | ||
4 | sif_sync_ena | When asserted enable SIF_SYNC mode. | 0 | ||
3 | alarm_2away_ena | When asserted, alarms from the FIFO that represent the pointers being 2 away are enabled. | 1 | ||
2 | alarm_1away_ena | When asserted, alarms from the FIFO that represent the pointers being 1 away are enabled. | 1 | ||
1 | alarm_collision_ena | When asserted, the collision of FIFO pointers causes an alarm to be generated. | 1 | ||
0 | reserved | Reserved | 0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
reserved | lvdsdata_ena | ||||||||||||||
R-0 | R-0 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config2 | 0x02 | 15 | reserved | Reserved | 0 |
14 | reserved | Reserved | 0 | ||
13:0 | lvdsdata_ena | These 14 bits are individual enables for the 14 input pin receivers: bits(13:7) turn on Da(6:0), where as bits(6:0) enable Db(6:0). | 0x3FFF |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
datadlya | clkdlya | datadlyb | clkdlyb | extref_ ena | reserved | dual_ clock_ena | |||||||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R-0 | R-0 | R/W-0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
datadlya | clkdlya | datadlyb | |||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
datadlyb | clkdlyb | extref_ ena | reserved | dual_ clock_ena | |||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R-0 | R-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config3 | 0x03 | 15:13 | datadlya | Controls the delay of the D[13:7]P/N inputs through the LVDS receivers for single bus mode; controls the delay of the DA[6:0]P/N inputs through the LVDS receivers for dual bus mode. 0 = no additional delay and each LSB adds a nominal 80 ps. |
000 |
12:10 | clkdlya | Controls the delay of the SYNCP/N inputs through the LVDS receivers for single bus mode; controls the delay of the DA_CLKP/N inputs through the LVDS receivers for dual bus mode. 0 = no additional delay and each LSB adds a nominal 80 ps. |
000 | ||
9:7 | datadlyb | Controls the delay of the D[6:0]P/N inputs through the LVDS receivers for single bus mode; controls the delay of the DB[6:0]P/N inputs through the LVDS receivers for dual bus mode. 0 = no additional delay and each LSB adds a nominal 80 ps. |
000 | ||
6:4 | clkdlyb | Controls the delay of the DATACLKP/N inputs through the LVDS receivers for single bus mode; controls the delay of the DB_CLKP/N inputs through the LVDS receivers for dual bus mode. 0 = no additional delay and each LSB adds a nominal 80 ps. |
000 | ||
3 | extref_ ena | Enables external reference for the DAC when set. | 0 | ||
2:1 | reserved | Reserved | 00 | ||
0 | dual_ clock_ena | When asserted it tells the LVDS input circuit that there are two individual data clocks. NOTE: Must be in SIF_SYNC mode. | 0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
reserved | iotest_ results | ||||||||||||||
R-0 | R-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config4 (WRITE TO CLEAR/No RESET Value) |
0x04 | 15:14 | reserved | Reserved | 00 |
13:0 | iotest_ results | The values of these bits tell which bit in the input word failed during the io-test pattern comparison. [13:7] match up with the 7 bits from port A and [6:0] match up with bits from port B. | 0x0000 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
alarm_from_ zerochka | alarm_from_ zerochkb | alarms_from_ fifoa | alarms_from_ fifob | ||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
alarm_dacclk_ gone | alarm_dataclk_ gone | clock_gone | alarm_from_ iotesta | alarm_from_ iotestb | reserved | ||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config5 (WRITE TO CLEAR) | 0x05 | 15 | alarm_from_ zerochka | When this bit is asserted the FIFO A write pointer has an all zeros pattern in it. Because this pointer is a shift register, all zeros cause the input point to be stuck until the next sync. The result could be a repeated 8T pattern at the output if the mixer is off and no syncs occur. Check for this error tells the user that another sync is necessary to restart the FIFO write pointer. | 0 |
14 | alarm_from_ zerochkb | When this bit is asserted the FIFO B write pointer has an all zeros pattern in it. Because this pointer is a shift register, all zeros cause the input point to be stuck until the next sync. The result could be a repeated 8T pattern at the output if the mixer is off and no syncs occur. Check for this error tells the user that another sync is necessary to restart the FIFO write pointer. | 0 | ||
13:11 | alarms_from_ fifoa | These bits report the FIFO A pointer status: 000: all fine, 001: pointers are 2 away, 01x: pointers are 1 away, 1xx: FIFO pointer collision. |
000 | ||
10:8 | alarms_from_ fifob | These bits report the FIFO B pointer status: 000: all fine 001: pointers are 2 away 01x: pointers are 1 away 1xx: FIFO pointer collision |
0 | ||
7 | alarm_dacclk_ gone | Bit gets asserted when the DACCLK has been stopped long for enough cycles to be caught. The number of cycles varies with interpolation. | 0 | ||
6 | alarm_dataclk_ gone | Bit gets asserted when the DATACLK has been stopped long for enough cycles to be caught. The number of cycles varies with interpolation. | 0 | ||
5 | clock_gone | This bit gets set when either alarm_dacclk_gone or alarm_dataclk_gone are asserted. It controls the output of the CDRV_SER block. When high, the CDRV_SER block outputs 0x8000 for each output connected to a DAC. The bit must be written to 0 for CDRV_SER outputs to resume normal operation. | 0 | ||
4 | alarm_from_ iotesta | This is asserted when the input data pattern does not match the pattern in the iotest_pattern registers. | 0 | ||
3 | alarm_from_ iotestb | This is asserted when the input data pattern does not match the pattern in the iotest_pattern registers. | 0 | ||
2 | reserved | Reserved | 0 | ||
1 | reserved | Reserved | 0 | ||
0 | reserved | Reserved | 0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
tempdata | |||||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
fuse_cntl | reserved | ||||||
R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config6 (No RESET value) |
0x06 | 15:8 | tempdata | This the output from the chip temperature sensor. NOTE: When reading these bits, the SIF interface must be extremely slow (1-MHz range). |
0x00 |
7:2 | fuse_cntl | These are the values of the blown fuses and are used to determine the available functionality in the chip. NOTE: These bits are READ_ONLY and allow the user to check what features have been disabled in the device: bit5 = 1: forces full word interface bit4 = 1: reserved bit3 = 1: reserved bit2 = 1: forces single DAC mode. NOTE: This does not force the channel B in sleep mode. To do so, the user is required to program the sleepb SPI bit (config10, bit 5) to 1 bit1 = 0: Forces a different bits size; 00 = 14-bit 01 = 12-bit 10 = 10-bit 11 = 10-bit |
0x00 | ||
1 | reserved | Reserved | 0 | ||
0 | reserved | Reserved | 0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
alarms_ mask | |||||||||||||||
R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config7 | 0x07 | 15:0 | alarms_ mask | Each bit is used to mask an alarm. Assertion masks the alarm: bit15 = alarm_mask_zerochka bit14 = alarm_mask_zerochkb bit13 = alarm_mask_fifoa_collision bit12 = alarm_mask_fifoa_1away bit11 = alarm_mask_fifoa_2away bit10 = alarm_mask_fifob_collision bit9 = alarm_mask_fifob_1away bit8 = alarm_mask_fifob_2away bit7 = alarm_mask_dacclk_gone bit6 = alarm_mask_dataclk_gone bit5 = masks the signal which turns off the DAC output when a clock or collision occurs (this bit has no effect on the PAD_ALARM output), bit4 = alarm_mask_iotesta bit3 = alarm_mask_iotestb bit2 = reserved bit1 = reserved bit0 = reserved |
0xFFFF |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
reserved | qmc_ offseta | ||||||||||||||
R/W-0 | R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config8 | 0x08 | 15:13 | reserved | Reserved | 010 |
12:0 | qmc_ offseta | The DAC A offset correction. The offset is measured in DAC LSBs. | 0x0000 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
fifo_ offset | qmc_ offsetb | ||||||||||||||
R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config9 (AUTO SYNC) |
0x09 | 15:13 | fifo_ offset | This is the starting point for the READ_POINTER in the FIFO block. The READ_POINTER is set to this location when a sync occurs on the DACCLK side of the FIFO. | 100 |
12:0 | qmc_ offsetb | The DAC B offset correction. The offset is measured in DAC LSBs. NOTE: Writing this register causes an autosync to be generated in the QMOFFSET block. | 0x0000 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
coarse_ dac | fuse_ sleep | reserved | reserved | tsense_ sleep | |||
R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
clkrecv_ ena | sleepa | sleepb | reserved | ||||
R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config10 | 0x0A | 15:12 | coarse_ dac | Scales the output current in 16 equal steps. | 1111 |
11 | fuse_ sleep | Put the fuses to sleep when set high. | 0 | ||
10 | reserved | Reserved | 0 | ||
9 | reserved | Reserved | 0 | ||
8 | tsense_ sleep | When asserted the temperature sensor is put to sleep. | 0 | ||
7 | clkrecv_ ena | Turn on the DAC CLOCK receiver block when asserted. | 1 | ||
6 | sleepa | When asserted DACA is put to sleep. | 0 | ||
5 | sleepb | When asserted DACB is put to sleep. NOTE: This bit is required to be programmed to 1 for single DAC mode. | 0 | ||
4:0 | reserved | Reserved | 00000 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
reserved | reserved | reserved | reserved | ||||||||||||
R-0 | R-0 | R-0 | R-1 | R-0 | R-0 | R-0 | R-1 | R-0 | R-0 | R-0 | R-1 | R-0 | R-0 | R-0 | R-1 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config11 | 0x0B | 15:12 | reserved | Reserved | 0001 |
11:8 | reserved | Reserved | 0001 | ||
7:4 | reserved | Reserved | 0001 | ||
3:0 | reserved | Reserved | 0001 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
reserved | iotest_ pattern0 | ||||||||||||||
R-0 | R-0 | R/W-1 | R/W-1 | R/W-1 | R/W-0 | R/W-1 | R/W-0 | R/W-0 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-0 | R/W-1 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config12 | 0x0C | 15:14 | reserved | Reserved | 00 |
13:0 | iotest_ pattern0 | This is dataword0 in the IO test pattern. It is used with the seven other words to test the input data. NOTE: This word must be aligned with the rising edge of SYNC when testing the IO interface. | 0x3A7A |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
reserved | iotest_ pattern1 | ||||||||||||||
R-0 | R-0 | R/W-1 | R/W-1 | R/W-0 | R/W-1 | R/W-1 | R/W-0 | R/W-1 | R/W-0 | R/W-1 | R/W-1 | R/W-0 | R/W-1 | R/W-1 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config13 | 0x0D | 15:14 | reserved | Reserved | 00 |
13:0 | iotest_ pattern1 | This is dataword1 in the IO test pattern. It is used with the seven other words to test the input data. | 0x36B6 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
reserved | iotest_ pattern2 | ||||||||||||||
R-0 | R-0 | R/W-1 | R/W-0 | R/W-1 | R/W-0 | R/W-1 | R/W-0 | R/W-1 | R/W-1 | R/W-1 | R/W-0 | R/W-1 | R/W-0 | R/W-1 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config14 | 0x0E | 15:14 | reserved | Reserved | 00 |
13:0 | iotest_ pattern2 | This is dataword2 in the IO test pattern. It is used with the seven other words to test the input data. | 0x2AEA |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
reserved | iotest_ pattern3 | ||||||||||||||
R-0 | R-0 | R/W-0 | R/W-0 | R/W-0 | R/W-1 | R/W-0 | R/W-1 | R/W-0 | R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-1 | R/W-0 | R/W-1 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config15 | 0x0F | 15:14 | reserved | Reserved | 00 |
13:0 | iotest_ pattern3 | This is dataword3 in the IO test pattern. It is used with the seven other words to test the input data. | 0x0545 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
reserved | iotest_ pattern4 | ||||||||||||||
R-0 | R-0 | R/W-0 | R/W-0 | R/W-0 | R/W-1 | R/W-0 | R/W-1 | R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-1 | R/W-0 | R/W-1 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config16 | 0x10 | 15:14 | reserved | Reserved | 00 |
13:0 | iotest_ pattern4 | This is dataword4 in the IO test pattern. It is used with the seven other words to test the input data. | 0x0585 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
reserved | iotest_ pattern5 | ||||||||||||||
R-0 | R-0 | R/W-0 | R/W-0 | R/W-1 | R/W-0 | R/W-0 | R/W-1 | R/W-0 | R/W-1 | R/W-0 | R/W-0 | R/W-1 | R/W-0 | R/W-0 | R/W-1 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config17 | 0x11 | 15:14 | reserved | Reserved | 00 |
13:0 | iotest_ pattern5 | This is dataword5 in the IO test pattern. It is used with the seven other words to test the input data. | 0x0949 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
reserved | iotest_ pattern6 | ||||||||||||||
R-0 | R-0 | R/W-0 | R/W-1 | R/W-0 | R/W-1 | R/W-0 | R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-1 | R/W-0 | R/W-1 | R/W-0 | R/W-1 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config18 | 0x12 | 15:14 | reserved | Reserved | 00 |
13:0 | iotest_ pattern6 | This is dataword6 in the IO test pattern. It is used with the seven other words to test the input data. | 0x1515 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
reserved | iotest_ pattern7 | ||||||||||||||
R-0 | R-0 | R/W-1 | R/W-1 | R/W-1 | R/W-0 | R/W-1 | R/W-0 | R/W-1 | R/W-0 | R/W-1 | R/W-1 | R/W-1 | R/W-0 | R/W-1 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config19 | 0x13 | 15:14 | reserved | Reserved | 00 |
13:0 | iotest_ pattern7 | This is dataword7 in the IO test pattern. It is used with the seven other words to test the input data. | 0x3ABA |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
sifdac_ ena | reserved | sifdac | |||||||||||||
R/W-0 | R-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config20 | 0x14 | 15 | sifdac_ ena | When asserted the DAC output is set to the value in sifdac. This can be used for trim setting and other static tests. | 0 |
14 | reserved | Reserved | 0 | ||
13:0 | sifdac | This is the value that is sent to the DACs when sifdac_ena is asserted. | 0x0000 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
sleepcntl | |||||||||||||||
R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config21 | 0x15 | 15:0 | sleepcntl | This controls what blocks is sent a SLEEP signal when the PAD_SLEEP pin is asserted. Programming a 1 in a bit passes the SLEEP signal to the appropriate block: bit15 = DAC A bit14 = DAC B bit13 = FUSE sleep bit12 = temperature sensor bit11 = clock receiver bit10 = LVDS DATA receivers bit9 = LVDS SYNC receiver bit8 = PECL ALIGN receiver bit7 = LVDS DATACLK receiver bit6 = reserved bit5 = reserved bit4 = reserved bit3 = reserved bit2 = reserved bit1 = reserved bit0 = reserved |
0xFFFF |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
fa002_ data(15:0) | |||||||||||||||
N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config22 (READ ONLY) |
0x16 | 15:0 | fa002_ data(15:0) | Lower 16 bits of the DIE ID word | N/A |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
fa002_ data(31:16) | |||||||||||||||
N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config23 (READ ONLY) |
0x17 | 15:0 | fa002_ data(31:16) | Lower-middle 16 bits of the DIE ID word | N/A |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
fa002_ data(47:32) | |||||||||||||||
N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config24 (READ ONLY) |
0x18 | 15:0 | fa002_ data(47:32) | Upper-middle 16 bits of the DIE ID word | N/A |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
fa002_ data(63:48) | |||||||||||||||
N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config25 (READ ONLY) |
0x19 | 15:0 | fa002_ data(63:48) | Upper 16 bits of the DIE ID word | N/A |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
reserved | reserved | reserved | reserved | ||||
R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
reserved | titest_voh | titest_vol | vendorid | versionid | |||
R-0 | R-1 | R-0 | R-0 | R-1 | R-0 | R-0 | R-1 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
REG NAME | ADDR (HEX) | BIT | NAME | FUNCTION | DEFAULT VALUE |
---|---|---|---|---|---|
config127 (READ ONLY and no RESET value) |
0x7F | 15:14 | reserved | Reserved | 00 |
13:12 | reserved | Reserved | 00 | ||
11:10 | reserved | Reserved | 00 | ||
9:8 | reserved | Reserved | 00 | ||
7 | reserved | Reserved | 0 | ||
6 | titest_voh | A fixed 1 that can be used to test the VOH at the SIF output | 1 | ||
5 | titest_vol | A fixed 0 that can be used to test the VOL at the SIF output | 0 | ||
4:3 | vendorid | Fixed at 01 | 01 | ||
2:0 | versionid | Chip version | 001 |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The DAC3174 is a single-channel, 14-bit, 500-MSPS DAC with a flexible input interface (full SDR, 14-bit interface; or DDR, 7-bit interface). DAC3174 supports independent input data clock and output DAC clock, and the FIFO can be used to absorb the timing difference of two clock domains. The DAC3174 can be widely used in many applications, such as real-IF transmitter for wireless infrastructure, arbitrary waveform generator, radar, cable head-end equipment, and so on.
Figure 56 below shows an example block diagram of the DAC3174 used as a real IF transmitter to generate a modulated communication signal.
A single-carrier, WCDMA-modulated waveform of 5-MHz bandwidth must be created. The WCDMA signal is modulated up to a 900-MHz carrier using a real mixer. A real mixer creates two images of the signal about the carrier frequency and some bleed-through of the local oscillator (LO); therefore, a band-pass filter is used to filter out the undesired signal image and the local oscillator.
The data pattern file that represents the desired 5-MHz, single-carrier, WCDMA signal is created with a pattern generation. Figure 56 shows the DAC3174 being clocked by an FPGA. The data pattern file is generated with the 5-MHz, WCDMA signal centered at an intermediate frequency of 100 MHz, and a local oscillator of 800 MHz is used to upconvert the modulated signal to 900 MHz. The real mixer creates an image of the desired signal centered about 700 MHz, and there is also a LO feedthrough spur present at 800 MHz. Figure 57 illustrates a band-pass filter following the mixer that is required to remove the lower image of the signal and the LO feedthrough spur.
The choice of the intermediate frequency has an impact on the design of the 900-MHz bandpass filter. The band-pass filter passes the WCDMA signal image that is centered at 900 MHz, but provides significant attenuation of the local oscillator feedthrough and the signal image. The distance between the signal and the image is equal to twice the intermediate frequency. If the intermediate frequency is too low, the image gets too close to the signal; therefore, a higher-order band-pass filter with steep rolloff is required. If the intermediate frequency is too high, the image is further away from the signal, but the signal is too far out towards the end of the Nyquist zone, and the sinx/x distortion becomes an issue. Centering the DAC output signal at an intermediate frequency of 100 MHz is a good, balanced choice in this example, and makes the design of the band-pass filter reasonably easy.
The DAC3174 does not have an interpolation option, so the data rate for the sample data are the same rate as the sample rate to the DAC3174. In this case, choose a sample rate of 500 MSPS (a commonly used telecommunications sample rate), so that the sample data rate into the DAC3174 is also 500 MSPS.
Figure 58 shows the DAC output ACPR of a single-carrier, WCDMA-modulated signal centered at an intermediate frequency of 100 MHz.
The DAC3174 uses as many as three different power-supply voltages. Some of the DAC power supplies are noise sensitive. Table 33 is a summary of the various power supplies of the DAC. See the evaluation module schematics for an example power-supply implementation. Take care to keep clean power supply routing away from noisy digital supplies. Avoid placing digital supplies and clean supplies on adjacent board layers and use a ground layer between noisy and clean supplies, if possible. All supplies pins must be decoupled as close to the pins as possible using small value capacitors, with larger bulk capacitors placed further away.
POWER SUPPLY | VOLTAGE | NOISE SENSITIVE | RECOMMENDATION |
---|---|---|---|
IOVDD | 1.8 V to 3.3 V | No | Digital supply (keep separate from noise-sensitive supplies) |
CLKVDD18 | 1.8 V | Yes | Provide clean voltage and avoid spurious noise |
DIGVDD18 | 1.8 V | No | Digital supply (keep separate from noise-sensitive supplies) |
VDDA18 | 1.8 V | Yes | Provide clean voltage and avoid spurious noise |
VDDDA33 | 3.3 V | Yes | Provide clean voltage and avoid spurious noise |
VFUSE | 1.8 V | No | Digital supply, connect to DIGVDD18 |